Struct esp32s3::rmt::int_st::R

pub struct R(_);

Register INT_ST reader

Implementations

impl R

pub unsafe fn ch_tx_end_int_st(&self, n: u8) -> CH_TX_END_INT_ST_R

The masked interrupt status bit for CH[0-3]_TX_END_INT.

pub fn ch0_tx_end_int_st(&self) -> CH_TX_END_INT_ST_R

Bit 0 - The masked interrupt status bit for CH0_TX_END_INT.

pub fn ch1_tx_end_int_st(&self) -> CH_TX_END_INT_ST_R

Bit 1 - The masked interrupt status bit for CH1_TX_END_INT.

pub fn ch2_tx_end_int_st(&self) -> CH_TX_END_INT_ST_R

Bit 2 - The masked interrupt status bit for CH2_TX_END_INT.

pub fn ch3_tx_end_int_st(&self) -> CH_TX_END_INT_ST_R

Bit 3 - The masked interrupt status bit for CH3_TX_END_INT.

pub unsafe fn ch_tx_err_int_st(&self, n: u8) -> CH_TX_ERR_INT_ST_R

The masked interrupt status bit for CH[0-3]_ERR_INT.

pub fn ch0_tx_err_int_st(&self) -> CH_TX_ERR_INT_ST_R

Bit 4 - The masked interrupt status bit for CH0_ERR_INT.

pub fn ch1_tx_err_int_st(&self) -> CH_TX_ERR_INT_ST_R

Bit 5 - The masked interrupt status bit for CH1_ERR_INT.

pub fn ch2_tx_err_int_st(&self) -> CH_TX_ERR_INT_ST_R

Bit 6 - The masked interrupt status bit for CH2_ERR_INT.

pub fn ch3_tx_err_int_st(&self) -> CH_TX_ERR_INT_ST_R

Bit 7 - The masked interrupt status bit for CH3_ERR_INT.

pub unsafe fn ch_tx_thr_event_int_st(&self, n: u8) -> CH_TX_THR_EVENT_INT_ST_R

The masked interrupt status bit for CH[0-3]_TX_THR_EVENT_INT.

pub fn ch0_tx_thr_event_int_st(&self) -> CH_TX_THR_EVENT_INT_ST_R

Bit 8 - The masked interrupt status bit for CH0_TX_THR_EVENT_INT.

pub fn ch1_tx_thr_event_int_st(&self) -> CH_TX_THR_EVENT_INT_ST_R

Bit 9 - The masked interrupt status bit for CH1_TX_THR_EVENT_INT.

pub fn ch2_tx_thr_event_int_st(&self) -> CH_TX_THR_EVENT_INT_ST_R

Bit 10 - The masked interrupt status bit for CH2_TX_THR_EVENT_INT.

pub fn ch3_tx_thr_event_int_st(&self) -> CH_TX_THR_EVENT_INT_ST_R

Bit 11 - The masked interrupt status bit for CH3_TX_THR_EVENT_INT.

pub unsafe fn ch_tx_loop_int_st(&self, n: u8) -> CH_TX_LOOP_INT_ST_R

The masked interrupt status bit for CH[0-3]_TX_LOOP_INT.

pub fn ch0_tx_loop_int_st(&self) -> CH_TX_LOOP_INT_ST_R

Bit 12 - The masked interrupt status bit for CH0_TX_LOOP_INT.

pub fn ch1_tx_loop_int_st(&self) -> CH_TX_LOOP_INT_ST_R

Bit 13 - The masked interrupt status bit for CH1_TX_LOOP_INT.

pub fn ch2_tx_loop_int_st(&self) -> CH_TX_LOOP_INT_ST_R

Bit 14 - The masked interrupt status bit for CH2_TX_LOOP_INT.

pub fn ch3_tx_loop_int_st(&self) -> CH_TX_LOOP_INT_ST_R

Bit 15 - The masked interrupt status bit for CH3_TX_LOOP_INT.

pub unsafe fn ch_rx_end_int_st(&self, n: u8) -> CH_RX_END_INT_ST_R

The masked interrupt status bit for CH4_RX_END_INT.

pub fn ch4_rx_end_int_st(&self) -> CH_RX_END_INT_ST_R

Bit 16 - The masked interrupt status bit for CH4_RX_END_INT.

pub fn ch5_rx_end_int_st(&self) -> CH_RX_END_INT_ST_R

Bit 17 - The masked interrupt status bit for CH4_RX_END_INT.

pub fn ch6_rx_end_int_st(&self) -> CH_RX_END_INT_ST_R

Bit 18 - The masked interrupt status bit for CH4_RX_END_INT.

pub fn ch7_rx_end_int_st(&self) -> CH_RX_END_INT_ST_R

Bit 19 - The masked interrupt status bit for CH4_RX_END_INT.

pub unsafe fn ch_rx_err_int_st(&self, n: u8) -> CH_RX_ERR_INT_ST_R

The masked interrupt status bit for CH4_ERR_INT.

pub fn ch4_rx_err_int_st(&self) -> CH_RX_ERR_INT_ST_R

Bit 20 - The masked interrupt status bit for CH4_ERR_INT.

pub fn ch5_rx_err_int_st(&self) -> CH_RX_ERR_INT_ST_R

Bit 21 - The masked interrupt status bit for CH4_ERR_INT.

pub fn ch6_rx_err_int_st(&self) -> CH_RX_ERR_INT_ST_R

Bit 22 - The masked interrupt status bit for CH4_ERR_INT.

pub fn ch7_rx_err_int_st(&self) -> CH_RX_ERR_INT_ST_R

Bit 23 - The masked interrupt status bit for CH4_ERR_INT.

pub fn ch4_rx_thr_event_int_st(&self) -> CH4_RX_THR_EVENT_INT_ST_R

Bit 24 - The masked interrupt status bit for CH4_RX_THR_EVENT_INT.

pub fn ch5_rx_thr_event_int_st(&self) -> CH5_RX_THR_EVENT_INT_ST_R

Bit 25 - The masked interrupt status bit for CH5_RX_THR_EVENT_INT.

pub fn ch6_rx_thr_event_int_st(&self) -> CH6_RX_THR_EVENT_INT_ST_R

Bit 26 - The masked interrupt status bit for CH6_RX_THR_EVENT_INT.

pub fn ch7_rx_thr_event_int_st(&self) -> CH7_RX_THR_EVENT_INT_ST_R

Bit 27 - The masked interrupt status bit for CH7_RX_THR_EVENT_INT.

pub fn tx_ch3_dma_access_fail_int_st(&self) -> TX_CH3_DMA_ACCESS_FAIL_INT_ST_R

Bit 28 - The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT.

pub fn rx_ch7_dma_access_fail_int_st(&self) -> RX_CH7_DMA_ACCESS_FAIL_INT_ST_R

Bit 29 - The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT.

Methods from Deref<Target = R<INT_ST_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<INT_ST_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<INT_ST_SPEC>> for R

fn from(reader: R<INT_ST_SPEC>) -> Self

Converts to this type from the input type.