Struct esp32s3::lcd_cam::lcd_clock::W

pub struct W(_);

Register LCD_CLOCK writer

Implementations

impl W

pub fn lcd_clkcnt_n(&mut self) -> LCD_CLKCNT_N_W<'_, 0>

Bits 0:5 - f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.

pub fn lcd_clk_equ_sysclk(&mut self) -> LCD_CLK_EQU_SYSCLK_W<'_, 6>

Bit 6 - 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).

pub fn lcd_ck_idle_edge(&mut self) -> LCD_CK_IDLE_EDGE_W<'_, 7>

Bit 7 - 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle.

pub fn lcd_ck_out_edge(&mut self) -> LCD_CK_OUT_EDGE_W<'_, 8>

Bit 8 - 1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock cycle.

pub fn lcd_clkm_div_num(&mut self) -> LCD_CLKM_DIV_NUM_W<'_, 9>

Bits 9:16 - Integral LCD clock divider value

pub fn lcd_clkm_div_b(&mut self) -> LCD_CLKM_DIV_B_W<'_, 17>

Bits 17:22 - Fractional clock divider numerator value

pub fn lcd_clkm_div_a(&mut self) -> LCD_CLKM_DIV_A_W<'_, 23>

Bits 23:28 - Fractional clock divider denominator value

pub fn lcd_clk_sel(&mut self) -> LCD_CLK_SEL_W<'_, 29>

Bits 29:30 - Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.

pub fn clk_en(&mut self) -> CLK_EN_W<'_, 31>

Bit 31 - Set this bit to enable clk gate

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<LCD_CLOCK_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<LCD_CLOCK_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<LCD_CLOCK_SPEC>> for W

fn from(writer: W<LCD_CLOCK_SPEC>) -> Self

Converts to this type from the input type.