Struct esp32s3::spi0::RegisterBlock
source · #[repr(C)]pub struct RegisterBlock {Show 38 fields
pub ctrl: CTRL,
pub ctrl1: CTRL1,
pub ctrl2: CTRL2,
pub clock: CLOCK,
pub user: USER,
pub user1: USER1,
pub user2: USER2,
pub rd_status: RD_STATUS,
pub ext_addr: EXT_ADDR,
pub misc: MISC,
pub cache_fctrl: CACHE_FCTRL,
pub cache_sctrl: CACHE_SCTRL,
pub sram_cmd: SRAM_CMD,
pub sram_drd_cmd: SRAM_DRD_CMD,
pub sram_dwr_cmd: SRAM_DWR_CMD,
pub sram_clk: SRAM_CLK,
pub fsm: FSM,
pub timing_cali: TIMING_CALI,
pub din_mode: DIN_MODE,
pub din_num: DIN_NUM,
pub dout_mode: DOUT_MODE,
pub spi_smem_timing_cali: SPI_SMEM_TIMING_CALI,
pub spi_smem_din_mode: SPI_SMEM_DIN_MODE,
pub spi_smem_din_num: SPI_SMEM_DIN_NUM,
pub spi_smem_dout_mode: SPI_SMEM_DOUT_MODE,
pub ecc_ctrl: ECC_CTRL,
pub ecc_err_addr: ECC_ERR_ADDR,
pub ecc_err_bit: ECC_ERR_BIT,
pub spi_smem_ac: SPI_SMEM_AC,
pub ddr: DDR,
pub spi_smem_ddr: SPI_SMEM_DDR,
pub clock_gate: CLOCK_GATE,
pub core_clk_sel: CORE_CLK_SEL,
pub int_ena: INT_ENA,
pub int_clr: INT_CLR,
pub int_raw: INT_RAW,
pub int_st: INT_ST,
pub date: DATE,
/* private fields */
}
Expand description
Register block
Fields§
§ctrl: CTRL
0x08 - SPI0 control register.
ctrl1: CTRL1
0x0c - SPI0 control 1 register.
ctrl2: CTRL2
0x10 - SPI0 control 2 register.
clock: CLOCK
0x14 - SPI_CLK clock division register when SPI0 accesses to flash.
user: USER
0x18 - SPI0 user register.
user1: USER1
0x1c - SPI0 user1 register.
user2: USER2
0x20 - SPI0 user2 register.
rd_status: RD_STATUS
0x2c - SPI0 read control register.
ext_addr: EXT_ADDR
0x30 - SPI0 extended address register.
misc: MISC
0x34 - SPI0 misc register
cache_fctrl: CACHE_FCTRL
0x3c - SPI0 external RAM bit mode control register.
cache_sctrl: CACHE_SCTRL
0x40 - SPI0 external RAM control register
sram_cmd: SRAM_CMD
0x44 - SPI0 external RAM mode control register
sram_drd_cmd: SRAM_DRD_CMD
0x48 - SPI0 external RAM DDR read command control register
sram_dwr_cmd: SRAM_DWR_CMD
0x4c - SPI0 external RAM DDR write command control register
sram_clk: SRAM_CLK
0x50 - SPI_CLK clock division register when SPI0 accesses to Ext_RAM.
fsm: FSM
0x54 - SPI0 state machine(FSM) status register.
timing_cali: TIMING_CALI
0xa8 - SPI0 timing compensation register when accesses to flash.
din_mode: DIN_MODE
0xac - MSPI input timing delay mode control register when accesses to flash.
din_num: DIN_NUM
0xb0 - MSPI input timing delay number control register when accesses to flash.
dout_mode: DOUT_MODE
0xb4 - MSPI output timing delay mode control register when accesses to flash.
spi_smem_timing_cali: SPI_SMEM_TIMING_CALI
0xbc - SPI0 Ext_RAM timing compensation register.
spi_smem_din_mode: SPI_SMEM_DIN_MODE
0xc0 - MSPI input timing delay mode control register when accesses to Ext_RAM.
spi_smem_din_num: SPI_SMEM_DIN_NUM
0xc4 - MSPI input timing delay number control register when accesses to Ext_RAM.
spi_smem_dout_mode: SPI_SMEM_DOUT_MODE
0xc8 - MSPI output timing delay mode control register when accesses to Ext_RAM.
ecc_ctrl: ECC_CTRL
0xcc - MSPI ECC control register
ecc_err_addr: ECC_ERR_ADDR
0xd0 - MSPI ECC error address register
ecc_err_bit: ECC_ERR_BIT
0xd4 - MSPI ECC error bits register
spi_smem_ac: SPI_SMEM_AC
0xdc - MSPI external RAM ECC and SPI CS timing control register
ddr: DDR
0xe0 - SPI0 flash DDR mode control register
spi_smem_ddr: SPI_SMEM_DDR
0xe4 - SPI0 external RAM DDR mode control register
clock_gate: CLOCK_GATE
0xe8 - SPI0 clk_gate register
core_clk_sel: CORE_CLK_SEL
0xec - SPI0 module clock select register
int_ena: INT_ENA
0xf0 - SPI1 interrupt enable register
int_clr: INT_CLR
0xf4 - SPI1 interrupt clear register
int_raw: INT_RAW
0xf8 - SPI1 interrupt raw register
int_st: INT_ST
0xfc - SPI1 interrupt status register
date: DATE
0x3fc - SPI0 version control register