Struct RegisterBlock

#[repr(C)]
pub struct RegisterBlock { /* private fields */ }

Register block

Implementations

impl RegisterBlock

pub const fn ctrl(&self) -> &CTRL

0x08 - SPI0 control register.

pub const fn ctrl1(&self) -> &CTRL1

0x0c - SPI0 control 1 register.

pub const fn ctrl2(&self) -> &CTRL2

0x10 - SPI0 control 2 register.

pub const fn clock(&self) -> &CLOCK

0x14 - SPI_CLK clock division register when SPI0 accesses to flash.

pub const fn user(&self) -> &USER

0x18 - SPI0 user register.

pub const fn user1(&self) -> &USER1

0x1c - SPI0 user1 register.

pub const fn user2(&self) -> &USER2

0x20 - SPI0 user2 register.

pub const fn rd_status(&self) -> &RD_STATUS

0x2c - SPI0 read control register.

pub const fn ext_addr(&self) -> &EXT_ADDR

0x30 - SPI0 extended address register.

pub const fn misc(&self) -> &MISC

0x34 - SPI0 misc register

pub const fn cache_fctrl(&self) -> &CACHE_FCTRL

0x3c - SPI0 external RAM bit mode control register.

pub const fn cache_sctrl(&self) -> &CACHE_SCTRL

0x40 - SPI0 external RAM control register

pub const fn sram_cmd(&self) -> &SRAM_CMD

0x44 - SPI0 external RAM mode control register

pub const fn sram_drd_cmd(&self) -> &SRAM_DRD_CMD

0x48 - SPI0 external RAM DDR read command control register

pub const fn sram_dwr_cmd(&self) -> &SRAM_DWR_CMD

0x4c - SPI0 external RAM DDR write command control register

pub const fn sram_clk(&self) -> &SRAM_CLK

0x50 - SPI_CLK clock division register when SPI0 accesses to Ext_RAM.

pub const fn fsm(&self) -> &FSM

0x54 - SPI0 state machine(FSM) status register.

pub const fn timing_cali(&self) -> &TIMING_CALI

0xa8 - SPI0 timing compensation register when accesses to flash.

pub const fn din_mode(&self) -> &DIN_MODE

0xac - MSPI input timing delay mode control register when accesses to flash.

pub const fn din_num(&self) -> &DIN_NUM

0xb0 - MSPI input timing delay number control register when accesses to flash.

pub const fn dout_mode(&self) -> &DOUT_MODE

0xb4 - MSPI output timing delay mode control register when accesses to flash.

pub const fn spi_smem_timing_cali(&self) -> &SPI_SMEM_TIMING_CALI

0xbc - SPI0 Ext_RAM timing compensation register.

pub const fn spi_smem_din_mode(&self) -> &SPI_SMEM_DIN_MODE

0xc0 - MSPI input timing delay mode control register when accesses to Ext_RAM.

pub const fn spi_smem_din_num(&self) -> &SPI_SMEM_DIN_NUM

0xc4 - MSPI input timing delay number control register when accesses to Ext_RAM.

pub const fn spi_smem_dout_mode(&self) -> &SPI_SMEM_DOUT_MODE

0xc8 - MSPI output timing delay mode control register when accesses to Ext_RAM.

pub const fn ecc_ctrl(&self) -> &ECC_CTRL

0xcc - MSPI ECC control register

pub const fn ecc_err_addr(&self) -> &ECC_ERR_ADDR

0xd0 - MSPI ECC error address register

pub const fn ecc_err_bit(&self) -> &ECC_ERR_BIT

0xd4 - MSPI ECC error bits register

pub const fn spi_smem_ac(&self) -> &SPI_SMEM_AC

0xdc - MSPI external RAM ECC and SPI CS timing control register

pub const fn ddr(&self) -> &DDR

0xe0 - SPI0 flash DDR mode control register

pub const fn spi_smem_ddr(&self) -> &SPI_SMEM_DDR

0xe4 - SPI0 external RAM DDR mode control register

pub const fn clock_gate(&self) -> &CLOCK_GATE

0xe8 - SPI0 clk_gate register

pub const fn core_clk_sel(&self) -> &CORE_CLK_SEL

0xec - SPI0 module clock select register

pub const fn int_ena(&self) -> &INT_ENA

0xf0 - SPI1 interrupt enable register

pub const fn int_clr(&self) -> &INT_CLR

0xf4 - SPI1 interrupt clear register

pub const fn int_raw(&self) -> &INT_RAW

0xf8 - SPI1 interrupt raw register

pub const fn int_st(&self) -> &INT_ST

0xfc - SPI1 interrupt status register

pub const fn date(&self) -> &DATE

0x3fc - SPI0 version control register