Struct esp32s3_hal::pac::lcd_cam::cam_ctrl1::W

pub struct W(_);

Register CAM_CTRL1 writer

Implementations

impl W

pub fn cam_rec_data_bytelen(
    &mut self
) -> FieldWriterRaw<'_, u32, CAM_CTRL1_SPEC, u16, u16, Unsafe, 16, 0>

Bits 0:15 - Camera receive data byte length minus 1 to set DMA in_suc_eof_int.

pub fn cam_line_int_num(
    &mut self
) -> FieldWriterRaw<'_, u32, CAM_CTRL1_SPEC, u8, u8, Unsafe, 6, 16>

Bits 16:21 - The line number minus 1 to generate cam_hs_int.

pub fn cam_clk_inv(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL1_SPEC, bool, BitM, 22>

Bit 22 - 1: Invert the input signal CAM_PCLK. 0: Not invert.

pub fn cam_vsync_filter_en(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL1_SPEC, bool, BitM, 23>

Bit 23 - 1: Enable CAM_VSYNC filter function. 0: bypass.

pub fn cam_2byte_en(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL1_SPEC, bool, BitM, 24>

Bit 24 - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8.

pub fn cam_de_inv(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL1_SPEC, bool, BitM, 25>

Bit 25 - CAM_DE invert enable signal, valid in high level.

pub fn cam_hsync_inv(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL1_SPEC, bool, BitM, 26>

Bit 26 - CAM_HSYNC invert enable signal, valid in high level.

pub fn cam_vsync_inv(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL1_SPEC, bool, BitM, 27>

Bit 27 - CAM_VSYNC invert enable signal, valid in high level.

pub fn cam_vh_de_mode_en(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL1_SPEC, bool, BitM, 28>

Bit 28 - 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 the the same time.

pub fn cam_start(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL1_SPEC, bool, BitM, 29>

Bit 29 - Camera module start signal.

pub fn cam_reset(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL1_SPEC, bool, BitM, 30>

Bit 30 - Camera module reset signal.

pub fn cam_afifo_reset(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL1_SPEC, bool, BitM, 31>

Bit 31 - Camera AFIFO reset signal.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<CAM_CTRL1_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CAM_CTRL1_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<CAM_CTRL1_SPEC>> for W

fn from(writer: W<CAM_CTRL1_SPEC>) -> W

Converts to this type from the input type.