Struct esp32s3_hal::pac::lcd_cam::cam_ctrl1::R
pub struct R(_);
Expand description
Register CAM_CTRL1
reader
Implementations§
§impl R
impl R
pub fn cam_rec_data_bytelen(&self) -> FieldReaderRaw<u16, u16>
pub fn cam_rec_data_bytelen(&self) -> FieldReaderRaw<u16, u16>
Bits 0:15 - Camera receive data byte length minus 1 to set DMA in_suc_eof_int.
pub fn cam_line_int_num(&self) -> FieldReaderRaw<u8, u8>
pub fn cam_line_int_num(&self) -> FieldReaderRaw<u8, u8>
Bits 16:21 - The line number minus 1 to generate cam_hs_int.
pub fn cam_clk_inv(&self) -> BitReaderRaw<bool>
pub fn cam_clk_inv(&self) -> BitReaderRaw<bool>
Bit 22 - 1: Invert the input signal CAM_PCLK. 0: Not invert.
pub fn cam_vsync_filter_en(&self) -> BitReaderRaw<bool>
pub fn cam_vsync_filter_en(&self) -> BitReaderRaw<bool>
Bit 23 - 1: Enable CAM_VSYNC filter function. 0: bypass.
pub fn cam_2byte_en(&self) -> BitReaderRaw<bool>
pub fn cam_2byte_en(&self) -> BitReaderRaw<bool>
Bit 24 - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8.
pub fn cam_de_inv(&self) -> BitReaderRaw<bool>
pub fn cam_de_inv(&self) -> BitReaderRaw<bool>
Bit 25 - CAM_DE invert enable signal, valid in high level.
pub fn cam_hsync_inv(&self) -> BitReaderRaw<bool>
pub fn cam_hsync_inv(&self) -> BitReaderRaw<bool>
Bit 26 - CAM_HSYNC invert enable signal, valid in high level.
pub fn cam_vsync_inv(&self) -> BitReaderRaw<bool>
pub fn cam_vsync_inv(&self) -> BitReaderRaw<bool>
Bit 27 - CAM_VSYNC invert enable signal, valid in high level.
pub fn cam_vh_de_mode_en(&self) -> BitReaderRaw<bool>
pub fn cam_vh_de_mode_en(&self) -> BitReaderRaw<bool>
Bit 28 - 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 the the same time.
Methods from Deref<Target = R<CAM_CTRL1_SPEC>>§
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.