Struct esp32s3_hal::pac::lcd_cam::cam_ctrl::W

pub struct W(_);

Register CAM_CTRL writer

Implementations

impl W

pub fn cam_stop_en(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL_SPEC, bool, BitM, 0>

Bit 0 - Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.

pub fn cam_vsync_filter_thres(
    &mut self
) -> FieldWriterRaw<'_, u32, CAM_CTRL_SPEC, u8, u8, Unsafe, 3, 1>

Bits 1:3 - Filter threshold value for CAM_VSYNC signal.

pub fn cam_update(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL_SPEC, bool, BitM, 4>

Bit 4 - 1: Update Camera registers, will be cleared by hardware. 0 : Not care.

pub fn cam_byte_order(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL_SPEC, bool, BitM, 5>

Bit 5 - 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.

pub fn cam_bit_order(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL_SPEC, bool, BitM, 6>

Bit 6 - 1: invert data byte order, only valid in 2 byte mode. 0: Not change.

pub fn cam_line_int_en(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL_SPEC, bool, BitM, 7>

Bit 7 - 1: Enable to generate CAM_HS_INT. 0: Disable.

pub fn cam_vs_eof_en(
    &mut self
) -> BitWriterRaw<'_, u32, CAM_CTRL_SPEC, bool, BitM, 8>

Bit 8 - 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen.

pub fn cam_clkm_div_num(
    &mut self
) -> FieldWriterRaw<'_, u32, CAM_CTRL_SPEC, u8, u8, Unsafe, 8, 9>

Bits 9:16 - Integral Camera clock divider value

pub fn cam_clkm_div_b(
    &mut self
) -> FieldWriterRaw<'_, u32, CAM_CTRL_SPEC, u8, u8, Unsafe, 6, 17>

Bits 17:22 - Fractional clock divider numerator value

pub fn cam_clkm_div_a(
    &mut self
) -> FieldWriterRaw<'_, u32, CAM_CTRL_SPEC, u8, u8, Unsafe, 6, 23>

Bits 23:28 - Fractional clock divider denominator value

pub fn cam_clk_sel(
    &mut self
) -> FieldWriterRaw<'_, u32, CAM_CTRL_SPEC, u8, u8, Unsafe, 2, 29>

Bits 29:30 - Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<CAM_CTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CAM_CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<CAM_CTRL_SPEC>> for W

fn from(writer: W<CAM_CTRL_SPEC>) -> W

Converts to this type from the input type.