Module esp32c6::timg0::wdtconfig0

Watchdog timer configuration register

Structs

• R
  Register WDTCONFIG0 reader
• W
  Register WDTCONFIG0 writer
• WDTCONFIG0_SPEC
  Watchdog timer configuration register

Type Definitions

• WDT_APPCPU_RESET_EN_R
  Field WDT_APPCPU_RESET_EN reader - WDT reset CPU enable.
• WDT_APPCPU_RESET_EN_W
  Field WDT_APPCPU_RESET_EN writer - WDT reset CPU enable.
• WDT_CONF_UPDATE_EN_W
  Field WDT_CONF_UPDATE_EN writer - update the WDT configuration registers
• WDT_CPU_RESET_LENGTH_R
  Field WDT_CPU_RESET_LENGTH reader - CPU reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
• WDT_CPU_RESET_LENGTH_W
  Field WDT_CPU_RESET_LENGTH writer - CPU reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
• WDT_EN_R
  Field WDT_EN reader - When set, MWDT is enabled.
• WDT_EN_W
  Field WDT_EN writer - When set, MWDT is enabled.
• WDT_FLASHBOOT_MOD_EN_R
  Field WDT_FLASHBOOT_MOD_EN reader - When set, Flash boot protection is enabled.
• WDT_FLASHBOOT_MOD_EN_W
  Field WDT_FLASHBOOT_MOD_EN writer - When set, Flash boot protection is enabled.
• WDT_PROCPU_RESET_EN_R
  Field WDT_PROCPU_RESET_EN reader - WDT reset CPU enable.
• WDT_PROCPU_RESET_EN_W
  Field WDT_PROCPU_RESET_EN writer - WDT reset CPU enable.
• WDT_STG0_R
  Field WDT_STG0 reader - Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
• WDT_STG0_W
  Field WDT_STG0 writer - Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
• WDT_STG1_R
  Field WDT_STG1 reader - Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
• WDT_STG1_W
  Field WDT_STG1 writer - Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
• WDT_STG2_R
  Field WDT_STG2 reader - Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
• WDT_STG2_W
  Field WDT_STG2 writer - Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
• WDT_STG3_R
  Field WDT_STG3 reader - Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
• WDT_STG3_W
  Field WDT_STG3 writer - Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
• WDT_SYS_RESET_LENGTH_R
  Field WDT_SYS_RESET_LENGTH reader - System reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
• WDT_SYS_RESET_LENGTH_W
  Field WDT_SYS_RESET_LENGTH writer - System reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
• WDT_USE_XTAL_R
  Field WDT_USE_XTAL reader - choose WDT clock:0-apb_clk, 1-xtal_clk.
• WDT_USE_XTAL_W
  Field WDT_USE_XTAL writer - choose WDT clock:0-apb_clk, 1-xtal_clk.