Type Alias esp32c3::spi2::slave::R

pub type R = R<SLAVE_SPEC>;

Register SLAVE reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn clk_mode(&self) -> CLK_MODE_R

Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.

pub fn clk_mode_13(&self) -> CLK_MODE_13_R

Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].

pub fn rsck_data_out(&self) -> RSCK_DATA_OUT_R

Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge

pub fn slv_rddma_bitlen_en(&self) -> SLV_RDDMA_BITLEN_EN_R

Bit 8 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others

pub fn slv_wrdma_bitlen_en(&self) -> SLV_WRDMA_BITLEN_EN_R

Bit 9 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others

pub fn slv_rdbuf_bitlen_en(&self) -> SLV_RDBUF_BITLEN_EN_R

Bit 10 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others

pub fn slv_wrbuf_bitlen_en(&self) -> SLV_WRBUF_BITLEN_EN_R

Bit 11 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others

pub fn dma_seg_magic_value(&self) -> DMA_SEG_MAGIC_VALUE_R

Bits 22:25 - The magic value of BM table in master DMA seg-trans.

pub fn mode(&self) -> MODE_R

Bit 26 - Set SPI work mode. 1: slave mode 0: master mode.

pub fn usr_conf(&self) -> USR_CONF_R

Bit 28 - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.