Type Alias esp32c3::spi2::clk_gate::W

pub type W = W<CLK_GATE_SPEC>;

Register CLK_GATE writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn clk_en(&mut self) -> CLK_EN_W<'_, CLK_GATE_SPEC>

Bit 0 - Set this bit to enable clk gate

pub fn mst_clk_active(&mut self) -> MST_CLK_ACTIVE_W<'_, CLK_GATE_SPEC>

Bit 1 - Set this bit to power on the SPI module clock.

pub fn mst_clk_sel(&mut self) -> MST_CLK_SEL_W<'_, CLK_GATE_SPEC>

Bit 2 - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.