Type Alias esp32c3::i2s0::tx_conf::R

pub type R = R<TX_CONF_SPEC>;

Register TX_CONF reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn tx_start(&self) -> TX_START_R

Bit 2 - Set this bit to start transmitting data

pub fn tx_slave_mod(&self) -> TX_SLAVE_MOD_R

Bit 3 - Set this bit to enable slave transmitter mode

pub fn tx_mono(&self) -> TX_MONO_R

Bit 5 - Set this bit to enable transmitter in mono mode

pub fn tx_chan_equal(&self) -> TX_CHAN_EQUAL_R

Bit 6 - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.

pub fn tx_big_endian(&self) -> TX_BIG_ENDIAN_R

Bit 7 - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.

pub fn tx_update(&self) -> TX_UPDATE_R

Bit 8 - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.

pub fn tx_mono_fst_vld(&self) -> TX_MONO_FST_VLD_R

Bit 9 - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.

pub fn tx_pcm_conf(&self) -> TX_PCM_CONF_R

Bits 10:11 - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &

pub fn tx_pcm_bypass(&self) -> TX_PCM_BYPASS_R

Bit 12 - Set this bit to bypass Compress/Decompress module for transmitted data.

pub fn tx_stop_en(&self) -> TX_STOP_EN_R

Bit 13 - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy

pub fn tx_left_align(&self) -> TX_LEFT_ALIGN_R

Bit 15 - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.

pub fn tx_24_fill_en(&self) -> TX_24_FILL_EN_R

Bit 16 - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode

pub fn tx_ws_idle_pol(&self) -> TX_WS_IDLE_POL_R

Bit 17 - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel.

pub fn tx_bit_order(&self) -> TX_BIT_ORDER_R

Bit 18 - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.

pub fn tx_tdm_en(&self) -> TX_TDM_EN_R

Bit 19 - 1: Enable I2S TDM Tx mode . 0: Disable.

pub fn tx_pdm_en(&self) -> TX_PDM_EN_R

Bit 20 - 1: Enable I2S PDM Tx mode . 0: Disable.

pub fn tx_chan_mod(&self) -> TX_CHAN_MOD_R

Bits 24:26 - I2S transmitter channel mode configuration bits.

pub fn sig_loopback(&self) -> SIG_LOOPBACK_R

Bit 27 - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.