Expand description
I2S TX configure register
Structs§
- I2S TX configure register
Type Aliases§
- Register
TX_CONF
reader - Field
SIG_LOOPBACK
reader - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. - Field
SIG_LOOPBACK
writer - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. - Field
TX_24_FILL_EN
reader - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode - Field
TX_24_FILL_EN
writer - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode - Field
TX_BIG_ENDIAN
reader - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. - Field
TX_BIG_ENDIAN
writer - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. - Field
TX_BIT_ORDER
reader - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. - Field
TX_BIT_ORDER
writer - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. - Field
TX_CHAN_EQUAL
reader - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. - Field
TX_CHAN_EQUAL
writer - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. - Field
TX_CHAN_MOD
reader - I2S transmitter channel mode configuration bits. - Field
TX_CHAN_MOD
writer - I2S transmitter channel mode configuration bits. - Field
TX_FIFO_RESET
writer - Set this bit to reset Tx AFIFO - Field
TX_LEFT_ALIGN
reader - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. - Field
TX_LEFT_ALIGN
writer - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. - Field
TX_MONO_FST_VLD
reader - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. - Field
TX_MONO_FST_VLD
writer - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. - Field
TX_MONO
reader - Set this bit to enable transmitter in mono mode - Field
TX_MONO
writer - Set this bit to enable transmitter in mono mode - Field
TX_PCM_BYPASS
reader - Set this bit to bypass Compress/Decompress module for transmitted data. - Field
TX_PCM_BYPASS
writer - Set this bit to bypass Compress/Decompress module for transmitted data. - Field
TX_PCM_CONF
reader - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & - Field
TX_PCM_CONF
writer - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & - Field
TX_PDM_EN
reader - 1: Enable I2S PDM Tx mode . 0: Disable. - Field
TX_PDM_EN
writer - 1: Enable I2S PDM Tx mode . 0: Disable. - Field
TX_RESET
writer - Set this bit to reset transmitter - Field
TX_SLAVE_MOD
reader - Set this bit to enable slave transmitter mode - Field
TX_SLAVE_MOD
writer - Set this bit to enable slave transmitter mode - Field
TX_START
reader - Set this bit to start transmitting data - Field
TX_START
writer - Set this bit to start transmitting data - Field
TX_STOP_EN
reader - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy - Field
TX_STOP_EN
writer - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy - Field
TX_TDM_EN
reader - 1: Enable I2S TDM Tx mode . 0: Disable. - Field
TX_TDM_EN
writer - 1: Enable I2S TDM Tx mode . 0: Disable. - Field
TX_UPDATE
reader - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. - Field
TX_UPDATE
writer - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. - Field
TX_WS_IDLE_POL
reader - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. - Field
TX_WS_IDLE_POL
writer - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. - Register
TX_CONF
writer