Struct esp32c2_hal::pac::uart0::clk_conf::R

pub struct R(_);

Register CLK_CONF reader

Implementations

impl R

pub fn sclk_div_b(&self) -> FieldReaderRaw<u8, u8>

Bits 0:5 - The denominator of the frequency divider factor.

pub fn sclk_div_a(&self) -> FieldReaderRaw<u8, u8>

Bits 6:11 - The numerator of the frequency divider factor.

pub fn sclk_div_num(&self) -> FieldReaderRaw<u8, u8>

Bits 12:19 - The integral part of the frequency divider factor.

pub fn sclk_sel(&self) -> FieldReaderRaw<u8, u8>

Bits 20:21 - UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.

pub fn sclk_en(&self) -> BitReaderRaw<bool>

Bit 22 - Set this bit to enable UART Tx/Rx clock.

pub fn rst_core(&self) -> BitReaderRaw<bool>

Bit 23 - Write 1 then write 0 to this bit, reset UART Tx/Rx.

pub fn tx_sclk_en(&self) -> BitReaderRaw<bool>

Bit 24 - Set this bit to enable UART Tx clock.

pub fn rx_sclk_en(&self) -> BitReaderRaw<bool>

Bit 25 - Set this bit to enable UART Rx clock.

pub fn tx_rst_core(&self) -> BitReaderRaw<bool>

Bit 26 - Write 1 then write 0 to this bit, reset UART Tx.

pub fn rx_rst_core(&self) -> BitReaderRaw<bool>

Bit 27 - Write 1 then write 0 to this bit, reset UART Rx.

Methods from Deref<Target = R<CLK_CONF_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CLK_CONF_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<CLK_CONF_SPEC>> for R

fn from(reader: R<CLK_CONF_SPEC>) -> R

Converts to this type from the input type.