Struct esp32c2_hal::pac::spi2::user1::R
pub struct R(_);
Expand description
Register USER1
reader
Implementations§
§impl R
impl R
pub fn usr_dummy_cyclelen(&self) -> FieldReaderRaw<u8, u8>
pub fn usr_dummy_cyclelen(&self) -> FieldReaderRaw<u8, u8>
Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.
pub fn mst_wfull_err_end_en(&self) -> BitReaderRaw<bool>
pub fn mst_wfull_err_end_en(&self) -> BitReaderRaw<bool>
Bit 16 - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.
pub fn cs_setup_time(&self) -> FieldReaderRaw<u8, u8>
pub fn cs_setup_time(&self) -> FieldReaderRaw<u8, u8>
Bits 17:21 - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.
pub fn cs_hold_time(&self) -> FieldReaderRaw<u8, u8>
pub fn cs_hold_time(&self) -> FieldReaderRaw<u8, u8>
Bits 22:26 - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.
pub fn usr_addr_bitlen(&self) -> FieldReaderRaw<u8, u8>
pub fn usr_addr_bitlen(&self) -> FieldReaderRaw<u8, u8>
Bits 27:31 - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.
Methods from Deref<Target = R<USER1_SPEC>>§
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.