Struct esp32c2_hal::pac::spi2::ctrl::R
pub struct R(_);Expand description
Register CTRL reader
Implementations§
§impl R
impl R
pub fn dummy_out(&self) -> BitReaderRaw<bool>
pub fn dummy_out(&self) -> BitReaderRaw<bool>
Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.
pub fn faddr_dual(&self) -> BitReaderRaw<bool>
pub fn faddr_dual(&self) -> BitReaderRaw<bool>
Bit 5 - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
pub fn faddr_quad(&self) -> BitReaderRaw<bool>
pub fn faddr_quad(&self) -> BitReaderRaw<bool>
Bit 6 - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
pub fn faddr_oct(&self) -> BitReaderRaw<bool>
pub fn faddr_oct(&self) -> BitReaderRaw<bool>
Bit 7 - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
pub fn fcmd_dual(&self) -> BitReaderRaw<bool>
pub fn fcmd_dual(&self) -> BitReaderRaw<bool>
Bit 8 - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
pub fn fcmd_quad(&self) -> BitReaderRaw<bool>
pub fn fcmd_quad(&self) -> BitReaderRaw<bool>
Bit 9 - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
pub fn fcmd_oct(&self) -> BitReaderRaw<bool>
pub fn fcmd_oct(&self) -> BitReaderRaw<bool>
Bit 10 - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
pub fn fread_dual(&self) -> BitReaderRaw<bool>
pub fn fread_dual(&self) -> BitReaderRaw<bool>
Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.
pub fn fread_quad(&self) -> BitReaderRaw<bool>
pub fn fread_quad(&self) -> BitReaderRaw<bool>
Bit 15 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.
pub fn fread_oct(&self) -> BitReaderRaw<bool>
pub fn fread_oct(&self) -> BitReaderRaw<bool>
Bit 16 - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.
pub fn q_pol(&self) -> BitReaderRaw<bool>
pub fn q_pol(&self) -> BitReaderRaw<bool>
Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.
pub fn d_pol(&self) -> BitReaderRaw<bool>
pub fn d_pol(&self) -> BitReaderRaw<bool>
Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.
pub fn hold_pol(&self) -> BitReaderRaw<bool>
pub fn hold_pol(&self) -> BitReaderRaw<bool>
Bit 20 - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
pub fn wp_pol(&self) -> BitReaderRaw<bool>
pub fn wp_pol(&self) -> BitReaderRaw<bool>
Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
pub fn rd_bit_order(&self) -> FieldReaderRaw<u8, u8>
pub fn rd_bit_order(&self) -> FieldReaderRaw<u8, u8>
Bits 23:24 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.
pub fn wr_bit_order(&self) -> FieldReaderRaw<u8, u8>
pub fn wr_bit_order(&self) -> FieldReaderRaw<u8, u8>
Bits 25:26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.
Methods from Deref<Target = R<CTRL_SPEC>>§
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.