Struct esp32c2_hal::pac::spi1::sus_status::R
pub struct R(_);
Expand description
Register SUS_STATUS
reader
Implementations§
§impl R
impl R
pub fn flash_sus(&self) -> BitReaderRaw<bool>
pub fn flash_sus(&self) -> BitReaderRaw<bool>
Bit 0 - The status of flash suspend, only used in SPI1.
pub fn wait_pesr_cmd_2b(&self) -> BitReaderRaw<bool>
pub fn wait_pesr_cmd_2b(&self) -> BitReaderRaw<bool>
Bit 1 - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
pub fn flash_hpm_dly_128(&self) -> BitReaderRaw<bool>
pub fn flash_hpm_dly_128(&self) -> BitReaderRaw<bool>
Bit 2 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.
pub fn flash_res_dly_128(&self) -> BitReaderRaw<bool>
pub fn flash_res_dly_128(&self) -> BitReaderRaw<bool>
Bit 3 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.
pub fn flash_dp_dly_128(&self) -> BitReaderRaw<bool>
pub fn flash_dp_dly_128(&self) -> BitReaderRaw<bool>
Bit 4 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.
pub fn flash_per_dly_128(&self) -> BitReaderRaw<bool>
pub fn flash_per_dly_128(&self) -> BitReaderRaw<bool>
Bit 5 - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.
pub fn flash_pes_dly_128(&self) -> BitReaderRaw<bool>
pub fn flash_pes_dly_128(&self) -> BitReaderRaw<bool>
Bit 6 - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.
pub fn spi0_lock_en(&self) -> BitReaderRaw<bool>
pub fn spi0_lock_en(&self) -> BitReaderRaw<bool>
Bit 7 - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
Methods from Deref<Target = R<SUS_STATUS_SPEC>>§
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.