Type Alias W

pub type W = W<CACHE_SCTRL_SPEC>;

Register CACHE_SCTRL writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn usr_sram_dio(&mut self) -> USR_SRAM_DIO_W<'_, CACHE_SCTRL_SPEC>

Bit 1 - For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable

pub fn usr_sram_qio(&mut self) -> USR_SRAM_QIO_W<'_, CACHE_SCTRL_SPEC>

Bit 2 - For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable

pub fn usr_wr_sram_dummy(&mut self) -> USR_WR_SRAM_DUMMY_W<'_, CACHE_SCTRL_SPEC>

Bit 3 - For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.

pub fn usr_rd_sram_dummy(&mut self) -> USR_RD_SRAM_DUMMY_W<'_, CACHE_SCTRL_SPEC>

Bit 4 - For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.

pub fn cache_sram_usr_rcmd( &mut self, ) -> CACHE_SRAM_USR_RCMD_W<'_, CACHE_SCTRL_SPEC>

Bit 5 - For SPI0 In the spi sram mode cache read sram for user define command.

pub fn sram_bytes_len(&mut self) -> SRAM_BYTES_LEN_W<'_, CACHE_SCTRL_SPEC>

Bits 6:13 - For SPI0 In the sram mode it is the byte length of spi read sram data.

pub fn sram_dummy_cyclelen( &mut self, ) -> SRAM_DUMMY_CYCLELEN_W<'_, CACHE_SCTRL_SPEC>

Bits 14:21 - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).

pub fn sram_addr_bitlen(&mut self) -> SRAM_ADDR_BITLEN_W<'_, CACHE_SCTRL_SPEC>

Bits 22:27 - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).

pub fn cache_sram_usr_wcmd( &mut self, ) -> CACHE_SRAM_USR_WCMD_W<'_, CACHE_SCTRL_SPEC>

Bit 28 - For SPI0 In the spi sram mode cache write sram for user define command