Module cache_sctrl
Source Expand description
- CACHE_SCTRL_SPEC
- You can
read
this register and get cache_sctrl::R
. You can reset
, write
, write_with_zero
this register using cache_sctrl::W
. You can also modify
this register. See API.
- CACHE_SRAM_USR_RCMD_R
- Field
CACHE_SRAM_USR_RCMD
reader - For SPI0 In the spi sram mode cache read sram for user define command. - CACHE_SRAM_USR_RCMD_W
- Field
CACHE_SRAM_USR_RCMD
writer - For SPI0 In the spi sram mode cache read sram for user define command. - CACHE_SRAM_USR_WCMD_R
- Field
CACHE_SRAM_USR_WCMD
reader - For SPI0 In the spi sram mode cache write sram for user define command - CACHE_SRAM_USR_WCMD_W
- Field
CACHE_SRAM_USR_WCMD
writer - For SPI0 In the spi sram mode cache write sram for user define command - R
- Register
CACHE_SCTRL
reader - SRAM_ADDR_BITLEN_R
- Field
SRAM_ADDR_BITLEN
reader - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1). - SRAM_ADDR_BITLEN_W
- Field
SRAM_ADDR_BITLEN
writer - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1). - SRAM_BYTES_LEN_R
- Field
SRAM_BYTES_LEN
reader - For SPI0 In the sram mode it is the byte length of spi read sram data. - SRAM_BYTES_LEN_W
- Field
SRAM_BYTES_LEN
writer - For SPI0 In the sram mode it is the byte length of spi read sram data. - SRAM_DUMMY_CYCLELEN_R
- Field
SRAM_DUMMY_CYCLELEN
reader - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1). - SRAM_DUMMY_CYCLELEN_W
- Field
SRAM_DUMMY_CYCLELEN
writer - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1). - USR_RD_SRAM_DUMMY_R
- Field
USR_RD_SRAM_DUMMY
reader - For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations. - USR_RD_SRAM_DUMMY_W
- Field
USR_RD_SRAM_DUMMY
writer - For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations. - USR_SRAM_DIO_R
- Field
USR_SRAM_DIO
reader - For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable - USR_SRAM_DIO_W
- Field
USR_SRAM_DIO
writer - For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable - USR_SRAM_QIO_R
- Field
USR_SRAM_QIO
reader - For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable - USR_SRAM_QIO_W
- Field
USR_SRAM_QIO
writer - For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable - USR_WR_SRAM_DUMMY_R
- Field
USR_WR_SRAM_DUMMY
reader - For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations. - USR_WR_SRAM_DUMMY_W
- Field
USR_WR_SRAM_DUMMY
writer - For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations. - W
- Register
CACHE_SCTRL
writer