Module esp32_hal::pac::spi0::sram_dwr_cmd

Structs

R

Register SRAM_DWR_CMD reader

SRAM_DWR_CMD_SPEC

This register you can read, write_with_zero, reset, write, modify. See API.

W

Register SRAM_DWR_CMD writer

Type Definitions

CACHE_SRAM_USR_WR_CMD_BITLEN_R

Field CACHE_SRAM_USR_WR_CMD_BITLEN reader - For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).

CACHE_SRAM_USR_WR_CMD_BITLEN_W

Field CACHE_SRAM_USR_WR_CMD_BITLEN writer - For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).

CACHE_SRAM_USR_WR_CMD_VALUE_R

Field CACHE_SRAM_USR_WR_CMD_VALUE reader - For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.

CACHE_SRAM_USR_WR_CMD_VALUE_W

Field CACHE_SRAM_USR_WR_CMD_VALUE writer - For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.