Struct esp32_hal::pac::rmt::chconf1::W

pub struct W(_);

Register CH%sCONF1 writer

Implementations

impl W

pub fn tx_start(&mut self) -> BitWriterRaw<'_, u32, CHCONF1_SPEC, bool, BitM, 0>

Bit 0 - Set this bit to start sending data for channel0.

pub fn rx_en(&mut self) -> BitWriterRaw<'_, u32, CHCONF1_SPEC, bool, BitM, 1>

Bit 1 - Set this bit to enbale receving data for channel0.

pub fn mem_wr_rst(
    &mut self
) -> BitWriterRaw<'_, u32, CHCONF1_SPEC, bool, BitM, 2>

Bit 2 - Set this bit to reset write ram address for channel0 by receiver access.

pub fn mem_rd_rst(
    &mut self
) -> BitWriterRaw<'_, u32, CHCONF1_SPEC, bool, BitM, 3>

Bit 3 - Set this bit to reset read ram address for channel0 by transmitter access.

pub fn apb_mem_rst(
    &mut self
) -> BitWriterRaw<'_, u32, CHCONF1_SPEC, bool, BitM, 4>

Bit 4 - Set this bit to reset W/R ram address for channel0 by apb fifo access

pub fn mem_owner(
    &mut self
) -> BitWriterRaw<'_, u32, CHCONF1_SPEC, bool, BitM, 5>

Bit 5 - This is the mark of channel0’s ram usage right.1’b1：receiver uses the ram 0：transmitter uses the ram

pub fn tx_conti_mode(
    &mut self
) -> BitWriterRaw<'_, u32, CHCONF1_SPEC, bool, BitM, 6>

Bit 6 - Set this bit to continue sending from the first data to the last data in channel0 again and again.

pub fn rx_filter_en(
    &mut self
) -> BitWriterRaw<'_, u32, CHCONF1_SPEC, bool, BitM, 7>

Bit 7 - This is the receive filter enable bit for channel0.

pub fn rx_filter_thres(
    &mut self
) -> FieldWriterRaw<'_, u32, CHCONF1_SPEC, u8, u8, Unsafe, 8, 8>

Bits 8:15 - in receive mode channel0 ignore input pulse when the pulse width is smaller then this value.

pub fn ref_cnt_rst(
    &mut self
) -> BitWriterRaw<'_, u32, CHCONF1_SPEC, bool, BitM, 16>

Bit 16 - This bit is used to reset divider in channel0.

pub fn ref_always_on(
    &mut self
) -> BitWriterRaw<'_, u32, CHCONF1_SPEC, bool, BitM, 17>

Bit 17 - This bit is used to select base clock. 1’b1:clk_apb 1’b0:clk_ref

pub fn idle_out_lv(
    &mut self
) -> BitWriterRaw<'_, u32, CHCONF1_SPEC, bool, BitM, 18>

Bit 18 - This bit configures the output signal’s level for channel0 in IDLE state.

pub fn idle_out_en(
    &mut self
) -> BitWriterRaw<'_, u32, CHCONF1_SPEC, bool, BitM, 19>

Bit 19 - This is the output enable control bit for channel0 in IDLE state.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<CHCONF1_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CHCONF1_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<CHCONF1_SPEC>> for W

fn from(writer: W<CHCONF1_SPEC>) -> W

Converts to this type from the input type.