Module esp32_hal::pac::rmt::chconf1

Structs

CHCONF1_SPEC

This register you can read, write_with_zero, reset, write, modify. See API.

R

Register CH%sCONF1 reader

W

Register CH%sCONF1 writer

Type Definitions

APB_MEM_RST_R

Field APB_MEM_RST reader - Set this bit to reset W/R ram address for channel0 by apb fifo access

APB_MEM_RST_W

Field APB_MEM_RST writer - Set this bit to reset W/R ram address for channel0 by apb fifo access

IDLE_OUT_EN_R

Field IDLE_OUT_EN reader - This is the output enable control bit for channel0 in IDLE state.

IDLE_OUT_EN_W

Field IDLE_OUT_EN writer - This is the output enable control bit for channel0 in IDLE state.

IDLE_OUT_LV_R

Field IDLE_OUT_LV reader - This bit configures the output signal’s level for channel0 in IDLE state.

IDLE_OUT_LV_W

Field IDLE_OUT_LV writer - This bit configures the output signal’s level for channel0 in IDLE state.

MEM_OWNER_R

Field MEM_OWNER reader - This is the mark of channel0’s ram usage right.1’b1：receiver uses the ram 0：transmitter uses the ram

MEM_OWNER_W

Field MEM_OWNER writer - This is the mark of channel0’s ram usage right.1’b1：receiver uses the ram 0：transmitter uses the ram

MEM_RD_RST_R

Field MEM_RD_RST reader - Set this bit to reset read ram address for channel0 by transmitter access.

MEM_RD_RST_W

Field MEM_RD_RST writer - Set this bit to reset read ram address for channel0 by transmitter access.

MEM_WR_RST_R

Field MEM_WR_RST reader - Set this bit to reset write ram address for channel0 by receiver access.

MEM_WR_RST_W

Field MEM_WR_RST writer - Set this bit to reset write ram address for channel0 by receiver access.

REF_ALWAYS_ON_R

Field REF_ALWAYS_ON reader - This bit is used to select base clock. 1’b1:clk_apb 1’b0:clk_ref

REF_ALWAYS_ON_W

Field REF_ALWAYS_ON writer - This bit is used to select base clock. 1’b1:clk_apb 1’b0:clk_ref

REF_CNT_RST_R

Field REF_CNT_RST reader - This bit is used to reset divider in channel0.

REF_CNT_RST_W

Field REF_CNT_RST writer - This bit is used to reset divider in channel0.

RX_EN_R

Field RX_EN reader - Set this bit to enbale receving data for channel0.

RX_EN_W

Field RX_EN writer - Set this bit to enbale receving data for channel0.

RX_FILTER_EN_R

Field RX_FILTER_EN reader - This is the receive filter enable bit for channel0.

RX_FILTER_EN_W

Field RX_FILTER_EN writer - This is the receive filter enable bit for channel0.

RX_FILTER_THRES_R

Field RX_FILTER_THRES reader - in receive mode channel0 ignore input pulse when the pulse width is smaller then this value.

RX_FILTER_THRES_W

Field RX_FILTER_THRES writer - in receive mode channel0 ignore input pulse when the pulse width is smaller then this value.

TX_CONTI_MODE_R

Field TX_CONTI_MODE reader - Set this bit to continue sending from the first data to the last data in channel0 again and again.

TX_CONTI_MODE_W

Field TX_CONTI_MODE writer - Set this bit to continue sending from the first data to the last data in channel0 again and again.

TX_START_R

Field TX_START reader - Set this bit to start sending data for channel0.

TX_START_W

Field TX_START writer - Set this bit to start sending data for channel0.