Struct esp32_hal::pac::dport::cache_ia_int_en::W

pub struct W(_);

Register CACHE_IA_INT_EN writer

Implementations

impl W

pub fn cache_ia_int_en(
    &mut self
) -> FieldWriterRaw<'_, u32, CACHE_IA_INT_EN_SPEC, u32, u32, Unsafe, 28, 0>

Bits 0:27 - Interrupt enable bits for various invalid cache access reasons

pub fn cache_ia_int_app_drom0(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_IA_INT_EN_SPEC, bool, BitM, 0>

Bit 0 - APP CPU invalid access to DROM0 when cache is disabled

pub fn cache_ia_int_app_iram0(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_IA_INT_EN_SPEC, bool, BitM, 1>

Bit 1 - APP CPU invalid access to IRAM0 when cache is disabled

pub fn cache_ia_int_app_iram1(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_IA_INT_EN_SPEC, bool, BitM, 2>

Bit 2 - APP CPU invalid access to IRAM1 when cache is disabled

pub fn cache_ia_int_app_irom0(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_IA_INT_EN_SPEC, bool, BitM, 3>

Bit 3 - APP CPU invalid access to IROM0 when cache is disabled

pub fn cache_ia_int_app_dram1(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_IA_INT_EN_SPEC, bool, BitM, 4>

Bit 4 - APP CPU invalid access to DRAM1 when cache is disabled

pub fn cache_ia_int_app_opposite(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_IA_INT_EN_SPEC, bool, BitM, 5>

Bit 5 - APP CPU invalid access to APP CPU cache when cache disabled

pub fn cache_ia_int_pro_drom0(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_IA_INT_EN_SPEC, bool, BitM, 14>

Bit 14 - PRO CPU invalid access to DROM0 when cache is disabled

pub fn cache_ia_int_pro_iram0(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_IA_INT_EN_SPEC, bool, BitM, 15>

Bit 15 - PRO CPU invalid access to IRAM0 when cache is disabled

pub fn cache_ia_int_pro_iram1(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_IA_INT_EN_SPEC, bool, BitM, 16>

Bit 16 - PRO CPU invalid access to IRAM1 when cache is disabled

pub fn cache_ia_int_pro_irom0(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_IA_INT_EN_SPEC, bool, BitM, 17>

Bit 17 - PRO CPU invalid access to IROM0 when cache is disabled

pub fn cache_ia_int_pro_dram1(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_IA_INT_EN_SPEC, bool, BitM, 18>

Bit 18 - PRO CPU invalid access to DRAM1 when cache is disabled

pub fn cache_ia_int_pro_opposite(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_IA_INT_EN_SPEC, bool, BitM, 19>

Bit 19 - PRO CPU invalid access to APP CPU cache when cache disabled

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<CACHE_IA_INT_EN_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CACHE_IA_INT_EN_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<CACHE_IA_INT_EN_SPEC>> for W

fn from(writer: W<CACHE_IA_INT_EN_SPEC>) -> W

Converts to this type from the input type.