Module esp32_hal::pac::dport::cache_ia_int_en
Expand description
Structs
Register
CACHE_IA_INT_EN
readerRegister
CACHE_IA_INT_EN
writerType Definitions
Field
CACHE_IA_INT_APP_DRAM1
reader - APP CPU invalid access to DRAM1 when cache is disabledField
CACHE_IA_INT_APP_DRAM1
writer - APP CPU invalid access to DRAM1 when cache is disabledField
CACHE_IA_INT_APP_DROM0
reader - APP CPU invalid access to DROM0 when cache is disabledField
CACHE_IA_INT_APP_DROM0
writer - APP CPU invalid access to DROM0 when cache is disabledField
CACHE_IA_INT_APP_IRAM0
reader - APP CPU invalid access to IRAM0 when cache is disabledField
CACHE_IA_INT_APP_IRAM0
writer - APP CPU invalid access to IRAM0 when cache is disabledField
CACHE_IA_INT_APP_IRAM1
reader - APP CPU invalid access to IRAM1 when cache is disabledField
CACHE_IA_INT_APP_IRAM1
writer - APP CPU invalid access to IRAM1 when cache is disabledField
CACHE_IA_INT_APP_IROM0
reader - APP CPU invalid access to IROM0 when cache is disabledField
CACHE_IA_INT_APP_IROM0
writer - APP CPU invalid access to IROM0 when cache is disabledField
CACHE_IA_INT_APP_OPPOSITE
reader - APP CPU invalid access to APP CPU cache when cache disabledField
CACHE_IA_INT_APP_OPPOSITE
writer - APP CPU invalid access to APP CPU cache when cache disabledField
CACHE_IA_INT_EN
reader - Interrupt enable bits for various invalid cache access reasonsField
CACHE_IA_INT_EN
writer - Interrupt enable bits for various invalid cache access reasonsField
CACHE_IA_INT_PRO_DRAM1
reader - PRO CPU invalid access to DRAM1 when cache is disabledField
CACHE_IA_INT_PRO_DRAM1
writer - PRO CPU invalid access to DRAM1 when cache is disabledField
CACHE_IA_INT_PRO_DROM0
reader - PRO CPU invalid access to DROM0 when cache is disabledField
CACHE_IA_INT_PRO_DROM0
writer - PRO CPU invalid access to DROM0 when cache is disabledField
CACHE_IA_INT_PRO_IRAM0
reader - PRO CPU invalid access to IRAM0 when cache is disabledField
CACHE_IA_INT_PRO_IRAM0
writer - PRO CPU invalid access to IRAM0 when cache is disabledField
CACHE_IA_INT_PRO_IRAM1
reader - PRO CPU invalid access to IRAM1 when cache is disabledField
CACHE_IA_INT_PRO_IRAM1
writer - PRO CPU invalid access to IRAM1 when cache is disabledField
CACHE_IA_INT_PRO_IROM0
reader - PRO CPU invalid access to IROM0 when cache is disabledField
CACHE_IA_INT_PRO_IROM0
writer - PRO CPU invalid access to IROM0 when cache is disabledField
CACHE_IA_INT_PRO_OPPOSITE
reader - PRO CPU invalid access to APP CPU cache when cache disabledField
CACHE_IA_INT_PRO_OPPOSITE
writer - PRO CPU invalid access to APP CPU cache when cache disabled