Struct esp32_hal::pac::dport::cache_ia_int_en::R
pub struct R(_);
Expand description
Register CACHE_IA_INT_EN
reader
Implementations§
§impl R
impl R
pub fn cache_ia_int_en(&self) -> FieldReaderRaw<u32, u32>
pub fn cache_ia_int_en(&self) -> FieldReaderRaw<u32, u32>
Bits 0:27 - Interrupt enable bits for various invalid cache access reasons
pub fn cache_ia_int_app_drom0(&self) -> BitReaderRaw<bool>
pub fn cache_ia_int_app_drom0(&self) -> BitReaderRaw<bool>
Bit 0 - APP CPU invalid access to DROM0 when cache is disabled
pub fn cache_ia_int_app_iram0(&self) -> BitReaderRaw<bool>
pub fn cache_ia_int_app_iram0(&self) -> BitReaderRaw<bool>
Bit 1 - APP CPU invalid access to IRAM0 when cache is disabled
pub fn cache_ia_int_app_iram1(&self) -> BitReaderRaw<bool>
pub fn cache_ia_int_app_iram1(&self) -> BitReaderRaw<bool>
Bit 2 - APP CPU invalid access to IRAM1 when cache is disabled
pub fn cache_ia_int_app_irom0(&self) -> BitReaderRaw<bool>
pub fn cache_ia_int_app_irom0(&self) -> BitReaderRaw<bool>
Bit 3 - APP CPU invalid access to IROM0 when cache is disabled
pub fn cache_ia_int_app_dram1(&self) -> BitReaderRaw<bool>
pub fn cache_ia_int_app_dram1(&self) -> BitReaderRaw<bool>
Bit 4 - APP CPU invalid access to DRAM1 when cache is disabled
pub fn cache_ia_int_app_opposite(&self) -> BitReaderRaw<bool>
pub fn cache_ia_int_app_opposite(&self) -> BitReaderRaw<bool>
Bit 5 - APP CPU invalid access to APP CPU cache when cache disabled
pub fn cache_ia_int_pro_drom0(&self) -> BitReaderRaw<bool>
pub fn cache_ia_int_pro_drom0(&self) -> BitReaderRaw<bool>
Bit 14 - PRO CPU invalid access to DROM0 when cache is disabled
pub fn cache_ia_int_pro_iram0(&self) -> BitReaderRaw<bool>
pub fn cache_ia_int_pro_iram0(&self) -> BitReaderRaw<bool>
Bit 15 - PRO CPU invalid access to IRAM0 when cache is disabled
pub fn cache_ia_int_pro_iram1(&self) -> BitReaderRaw<bool>
pub fn cache_ia_int_pro_iram1(&self) -> BitReaderRaw<bool>
Bit 16 - PRO CPU invalid access to IRAM1 when cache is disabled
pub fn cache_ia_int_pro_irom0(&self) -> BitReaderRaw<bool>
pub fn cache_ia_int_pro_irom0(&self) -> BitReaderRaw<bool>
Bit 17 - PRO CPU invalid access to IROM0 when cache is disabled
pub fn cache_ia_int_pro_dram1(&self) -> BitReaderRaw<bool>
pub fn cache_ia_int_pro_dram1(&self) -> BitReaderRaw<bool>
Bit 18 - PRO CPU invalid access to DRAM1 when cache is disabled
pub fn cache_ia_int_pro_opposite(&self) -> BitReaderRaw<bool>
pub fn cache_ia_int_pro_opposite(&self) -> BitReaderRaw<bool>
Bit 19 - PRO CPU invalid access to APP CPU cache when cache disabled
Methods from Deref<Target = R<CACHE_IA_INT_EN_SPEC>>§
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.