Struct RegisterBlock 

#[repr(C)]
pub struct RegisterBlock {

    pub spt_cfg: Reg<SPT_CFG_SPEC>,
    pub sleep_mode: Reg<SLEEP_MODE_SPEC>,
    pub error_cmp_40m: Reg<ERROR_CMP_40M_SPEC>,
    pub error_cmp_1s_0: Reg<ERROR_CMP_1S_0_SPEC>,
    pub error_cmp_1s_1: Reg<ERROR_CMP_1S_1_SPEC>,
    pub error_cmp_1s_2: Reg<ERROR_CMP_1S_2_SPEC>,
    pub error_cmp_1s_3: Reg<ERROR_CMP_1S_3_SPEC>,
    pub error_cmp_rtc_0: Reg<ERROR_CMP_RTC_0_SPEC>,
    pub error_cmp_rtc_1: Reg<ERROR_CMP_RTC_1_SPEC>,
    pub error_cmp_rtc_2: Reg<ERROR_CMP_RTC_2_SPEC>,
    pub error_cmp_rtc_3: Reg<ERROR_CMP_RTC_3_SPEC>,
    pub update_tmr_val: Reg<UPDATE_TMR_VAL_SPEC>,
    pub spare_bits: Reg<SPARE_BITS_SPEC>,
    pub timer_value: Reg<TIMER_VALUE_SPEC>,
    /* private fields */
}

Register block

Fields

spt_cfg: Reg<SPT_CFG_SPEC>

0x00 - Configuration register for the simple periodic timer

sleep_mode: Reg<SLEEP_MODE_SPEC>

0x04 - Allows blocking the PMU and FFE kickoff signal

error_cmp_40m: Reg<ERROR_CMP_40M_SPEC>

0x08 - 40 msec increment error compensation register

error_cmp_1s_0: Reg<ERROR_CMP_1S_0_SPEC>

0x0c - 1 sec Increment Error Compensation 0 Register

error_cmp_1s_1: Reg<ERROR_CMP_1S_1_SPEC>

0x10 - 1 sec Incremente Error Compensation 1 Register

error_cmp_1s_2: Reg<ERROR_CMP_1S_2_SPEC>

0x14 - 1 sec Incremente Error Compensation 2 Register

error_cmp_1s_3: Reg<ERROR_CMP_1S_3_SPEC>

0x18 - 1 sec Incremente Error Compensation 3 Register

error_cmp_rtc_0: Reg<ERROR_CMP_RTC_0_SPEC>

0x1c - 2, 4, 6, 8, 16 sec Increment Error Compensation Register

error_cmp_rtc_1: Reg<ERROR_CMP_RTC_1_SPEC>

0x20 - 32, 64, 128, 256 sec Increment Error Compensation Register

error_cmp_rtc_2: Reg<ERROR_CMP_RTC_2_SPEC>

0x24 - 512, 1024, 2048, 4096 sec Increment Error Compensation Register.

error_cmp_rtc_3: Reg<ERROR_CMP_RTC_3_SPEC>

0x28 - 8192, 16384 sec Increment Error Compensation Register

update_tmr_val: Reg<UPDATE_TMR_VAL_SPEC>

0x2c - Update the 30-Bit Timer once write. Note: Please programmed SPT_EN (0x000, bit 0) to 0 before write this register to avoid any potential issue

spare_bits: Reg<SPARE_BITS_SPEC>

0x30 - Not documented

timer_value: Reg<TIMER_VALUE_SPEC>

0x34 - Return the Value of 30-bits, in 1mS resoultion. This is the RTC value

Implementations

impl RegisterBlock

pub fn ms_cnt_value(&self) -> &Reg<MS_CNT_VALUE_SPEC>

0x38 - Return the Value of the 1mS counter which is generating the 1mS event. It is an downcount counter. Default is 0x40 (65-1). For 32KHz input, the resoultion is ~15uS. For 16KHz input, the resoultion is ~30uS

pub fn event_cnt_value(&self) -> &Reg<EVENT_CNT_VALUE_SPEC>

0x38 - Return the Value of the Event counter generating FFE Time out event It is an upcount counter, in 1mS resoultion.