pub struct W(/* private fields */);Expand description
Register CTRLR0 writer
Implementations§
Source§impl W
impl W
Sourcepub fn dfs(&mut self) -> DFS_W<'_>
pub fn dfs(&mut self) -> DFS_W<'_>
Bits 0:3 - Data Frame Size. Dependencies: When SSI_HC_FRF=1, SCPH bit is a read-only bit, with its value set by SSI_DFLT_SCPH. Selects the data frame length. When the data frame size is programmed to be less than 16 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You must right-justify transmit data before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. For the field decode, refer to Table 6-2.
Sourcepub fn scph(&mut self) -> SCPH_W<'_>
pub fn scph(&mut self) -> SCPH_W<'_>
Bit 6 - Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0, data are captured on the first edge of the serial clock. When SCPH = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. Dependencies: When SSI_HC_FRF=1, SCPH bit is a read-only bit, with its value set by SSI_DFLT_SCPH.
Sourcepub fn scpol(&mut self) -> SCPOL_W<'_>
pub fn scpol(&mut self) -> SCPOL_W<'_>
Bit 7 - Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the SPI Master is not actively transferring data on the serial bus. Dependencies: When SSI_HC_FRF=1, SCPOL bit is a read-only bit with its value set by SSI_DFLT_SCPOL.
Sourcepub fn tmod(&mut self) -> TMOD_W<'_>
pub fn tmod(&mut self) -> TMOD_W<'_>
Bits 8:9 - Transfer Mode. Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In transmit-only mode, data received from the external device is not valid and is not stored in the receive FIFO memory; it is overwritten on the next transfer. In receive-only mode, transmitted data are not valid. After the first write to the transmit FIFO, the same word is retransmitted for the duration of the transfer. In transmit-and-receive mode, both transmit and receive data are valid. The transfer continues until the transmit FIFO is empty. Data received from the external device are stored into the receive FIFO memory, where it can be accessed by the host processor. In eeprom-read mode, receive data is not valid while control data is being transmitted. When all control data is sent to the EEPROM, receive data becomes valid and transmit data becomes invalid. All data in the transmit FIFO is considered control data in this mode. This transfer mode is only valid when the SPI Master is configured as a master device.
Sourcepub fn slv_oe(&mut self) -> SLV_OE_W<'_>
pub fn slv_oe(&mut self) -> SLV_OE_W<'_>
Bit 10 - No function for SPI Master. Slave usage only.
Sourcepub fn srl(&mut self) -> SRL_W<'_>
pub fn srl(&mut self) -> SRL_W<'_>
Bit 11 - Shift Register Loop. Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input. Can be used in both serial slave and serial-master modes. When the SPI Master is configured as a slave in loopback mode, the ss_in_n and ssi_clk signals must be provided by an external source. In this mode, the slave cannot generate these signals because there is nothing to which to loop back.