RegisterBlock

Struct RegisterBlock

#[repr(C)]
pub struct RegisterBlock {Show 22 fields
    pub dma_status: Reg<DMA_STATUS_SPEC>,
    pub dma_cfg: Reg<DMA_CFG_SPEC>,
    pub ctrl_base_ptr: Reg<CTRL_BASE_PTR_SPEC>,
    pub alt_ctrl_base_ptr: Reg<ALT_CTRL_BASE_PTR_SPEC>,
    pub dma_waitonreq_status: Reg<DMA_WAITONREQ_STATUS_SPEC>,
    pub chnl_sw_req: Reg<CHNL_SW_REQ_SPEC>,
    pub chnl_use_burst_set: Reg<CHNL_USE_BURST_SET_SPEC>,
    pub chnl_useburst_set: Reg<CHNL_USEBURST_SET_SPEC>,
    pub chnl_req_mask_set: Reg<CHNL_REQ_MASK_SET_SPEC>,
    pub chnl_req_mask_clr: Reg<CHNL_REQ_MASK_CLR_SPEC>,
    pub chnl_enable_set: Reg<CHNL_ENABLE_SET_SPEC>,
    pub chnl_enable_clr: Reg<CHNL_ENABLE_CLR_SPEC>,
    pub chnl_pri_alt_set: Reg<CHNL_PRI_ALT_SET_SPEC>,
    pub chnl_pri_alt_clr: Reg<CHNL_PRI_ALT_CLR_SPEC>,
    pub chnl_priority_set: Reg<CHNL_PRIORITY_SET_SPEC>,
    pub chnl_priority_clear: Reg<CHNL_PRIORITY_CLEAR_SPEC>,
    pub err_clr: Reg<ERR_CLR_SPEC>,
    pub periph_id_4: Reg<PERIPH_ID_4_SPEC>,
    pub periph_id_0: Reg<PERIPH_ID_0_SPEC>,
    pub periph_id_1: Reg<PERIPH_ID_1_SPEC>,
    pub periph_id_2: Reg<PERIPH_ID_2_SPEC>,
    pub periph_id_3: Reg<PERIPH_ID_3_SPEC>,
    /* private fields */
}

Expand description

Register block

Fields§

§dma_status: Reg<DMA_STATUS_SPEC>

0x00 - DMA Status register

§dma_cfg: Reg<DMA_CFG_SPEC>

0x04 - DMA configuration register

§ctrl_base_ptr: Reg<CTRL_BASE_PTR_SPEC>

0x08 - Control the pointer to the base address of the primary data structure

§alt_ctrl_base_ptr: Reg<ALT_CTRL_BASE_PTR_SPEC>

0x0c - Base address of the alternate data structure.

§dma_waitonreq_status: Reg<DMA_WAITONREQ_STATUS_SPEC>

0x10 - Channel wait on request status

§chnl_sw_req: Reg<CHNL_SW_REQ_SPEC>

0x14 - Registers to generate a software DMA request in one of the 16 DMA channels

§chnl_use_burst_set: Reg<CHNL_USE_BURST_SET_SPEC>

0x18 - Returns the useburst status, or disables dma_sreq[Channel] from generating DMA requests

§chnl_useburst_set: Reg<CHNL_USEBURST_SET_SPEC>

0x1c - Set the appropriate bit to enable dma_sreq[Channel] to generate requests.

§chnl_req_mask_set: Reg<CHNL_REQ_MASK_SET_SPEC>

0x20 - Returns the request mask status of dma_req[] and dma_sreq[], or disables the corresponding channel from generating DMA requests.

§chnl_req_mask_clr: Reg<CHNL_REQ_MASK_CLR_SPEC>

0x24 - Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req[C] and dma_sreq[C].

§chnl_enable_set: Reg<CHNL_ENABLE_SET_SPEC>

0x28 - Returns the enable status of the channels, or enables the corresponding channels.

§chnl_enable_clr: Reg<CHNL_ENABLE_CLR_SPEC>

0x2c - Set the appropriate bit to disable the corresponding DMA channel.

§chnl_pri_alt_set: Reg<CHNL_PRI_ALT_SET_SPEC>

0x30 - Returns the channel control data structure status, or selects the alternate data structure for the corresponding DMA channel.

§chnl_pri_alt_clr: Reg<CHNL_PRI_ALT_CLR_SPEC>

0x34 - Set the appropriate bit to select the primary data structure for the corresponding DMA channel.

§chnl_priority_set: Reg<CHNL_PRIORITY_SET_SPEC>

0x38 - Returns the channel priority mask status, or sets the channel priority to high.

§chnl_priority_clear: Reg<CHNL_PRIORITY_CLEAR_SPEC>

0x3c - Set the appropriate bit to select the default priority level for the specified DMA channel.

§err_clr: Reg<ERR_CLR_SPEC>

0x4c - Returns the status of dma_err, or sets the signal LOW.

§periph_id_4: Reg<PERIPH_ID_4_SPEC>

0xfd0 - Peripheral identification 4

§periph_id_0: Reg<PERIPH_ID_0_SPEC>

0xfe0 - Peripheral identification 0

§periph_id_1: Reg<PERIPH_ID_1_SPEC>

0xfe4 - Peripheral identification 1

§periph_id_2: Reg<PERIPH_ID_2_SPEC>

0xfe8 - Peripheral identification 2

§periph_id_3: Reg<PERIPH_ID_3_SPEC>

0xfec - Peripheral identification 3

Implementations§

impl RegisterBlock

pub fn pcell_id_3(&self) -> &Reg<PCELL_ID_3_SPEC>

0xff0 - PrimeCell identification 3

pub fn pcell_id_2(&self) -> &Reg<PCELL_ID_2_SPEC>

0xff0 - PrimeCell identification 2

pub fn pcell_id_1(&self) -> &Reg<PCELL_ID_1_SPEC>

0xff0 - PrimeCell identification 1

pub fn pcell_id_0(&self) -> &Reg<PCELL_ID_0_SPEC>

0xff0 - PrimeCell identification 0

Auto Trait Implementations§

impl !Freeze for RegisterBlock

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations§

impl<T> Any for T
where T: 'static + ?Sized,

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impl<T> Borrow<T> for T
where T: ?Sized,

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impl<T> BorrowMut<T> for T
where T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

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impl<T> From<T> for T

fn from(t: T) -> T

Returns the argument unchanged.

impl<T, U> Into<U> for T
where U: From<T>,

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

impl<T, U> TryFrom<U> for T
where U: Into<T>,

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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.

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where U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.