1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - DMA Status register"]
5 pub dma_status: crate::Reg<dma_status::DMA_STATUS_SPEC>,
6 #[doc = "0x04 - DMA configuration register"]
7 pub dma_cfg: crate::Reg<dma_cfg::DMA_CFG_SPEC>,
8 #[doc = "0x08 - Control the pointer to the base address of the primary data structure"]
9 pub ctrl_base_ptr: crate::Reg<ctrl_base_ptr::CTRL_BASE_PTR_SPEC>,
10 #[doc = "0x0c - Base address of the alternate data structure."]
11 pub alt_ctrl_base_ptr:
12 crate::Reg<alt_ctrl_base_ptr::ALT_CTRL_BASE_PTR_SPEC>,
13 #[doc = "0x10 - Channel wait on request status"]
14 pub dma_waitonreq_status:
15 crate::Reg<dma_waitonreq_status::DMA_WAITONREQ_STATUS_SPEC>,
16 #[doc = "0x14 - Registers to generate a software DMA request in one of the 16 DMA channels"]
17 pub chnl_sw_req: crate::Reg<chnl_sw_req::CHNL_SW_REQ_SPEC>,
18 #[doc = "0x18 - Returns the useburst status, or disables dma_sreq\\[Channel\\]
19from generating DMA requests"]
20 pub chnl_use_burst_set:
21 crate::Reg<chnl_use_burst_set::CHNL_USE_BURST_SET_SPEC>,
22 #[doc = "0x1c - Set the appropriate bit to enable dma_sreq\\[Channel\\]
23to generate requests."]
24 pub chnl_useburst_set:
25 crate::Reg<chnl_useburst_set::CHNL_USEBURST_SET_SPEC>,
26 #[doc = "0x20 - Returns the request mask status of dma_req\\[\\]
27and dma_sreq\\[\\], or disables the corresponding channel from generating DMA requests."]
28 pub chnl_req_mask_set:
29 crate::Reg<chnl_req_mask_set::CHNL_REQ_MASK_SET_SPEC>,
30 #[doc = "0x24 - Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req\\[C\\]
31and dma_sreq\\[C\\]."]
32 pub chnl_req_mask_clr:
33 crate::Reg<chnl_req_mask_clr::CHNL_REQ_MASK_CLR_SPEC>,
34 #[doc = "0x28 - Returns the enable status of the channels, or enables the corresponding channels."]
35 pub chnl_enable_set: crate::Reg<chnl_enable_set::CHNL_ENABLE_SET_SPEC>,
36 #[doc = "0x2c - Set the appropriate bit to disable the corresponding DMA channel."]
37 pub chnl_enable_clr: crate::Reg<chnl_enable_clr::CHNL_ENABLE_CLR_SPEC>,
38 #[doc = "0x30 - Returns the channel control data structure status, or selects the alternate data structure for the corresponding DMA channel."]
39 pub chnl_pri_alt_set: crate::Reg<chnl_pri_alt_set::CHNL_PRI_ALT_SET_SPEC>,
40 #[doc = "0x34 - Set the appropriate bit to select the primary data structure for the corresponding DMA channel."]
41 pub chnl_pri_alt_clr: crate::Reg<chnl_pri_alt_clr::CHNL_PRI_ALT_CLR_SPEC>,
42 #[doc = "0x38 - Returns the channel priority mask status, or sets the channel priority to high."]
43 pub chnl_priority_set:
44 crate::Reg<chnl_priority_set::CHNL_PRIORITY_SET_SPEC>,
45 #[doc = "0x3c - Set the appropriate bit to select the default priority level for the specified DMA channel."]
46 pub chnl_priority_clear:
47 crate::Reg<chnl_priority_clear::CHNL_PRIORITY_CLEAR_SPEC>,
48 _reserved16: [u8; 0x0c],
49 #[doc = "0x4c - Returns the status of dma_err, or sets the signal LOW."]
50 pub err_clr: crate::Reg<err_clr::ERR_CLR_SPEC>,
51 _reserved17: [u8; 0x0f80],
52 #[doc = "0xfd0 - Peripheral identification 4"]
53 pub periph_id_4: crate::Reg<periph_id_4::PERIPH_ID_4_SPEC>,
54 _reserved18: [u8; 0x0c],
55 #[doc = "0xfe0 - Peripheral identification 0"]
56 pub periph_id_0: crate::Reg<periph_id_0::PERIPH_ID_0_SPEC>,
57 #[doc = "0xfe4 - Peripheral identification 1"]
58 pub periph_id_1: crate::Reg<periph_id_1::PERIPH_ID_1_SPEC>,
59 #[doc = "0xfe8 - Peripheral identification 2"]
60 pub periph_id_2: crate::Reg<periph_id_2::PERIPH_ID_2_SPEC>,
61 #[doc = "0xfec - Peripheral identification 3"]
62 pub periph_id_3: crate::Reg<periph_id_3::PERIPH_ID_3_SPEC>,
63 _reserved_22_pcell_id_: [u8; 0x04],
64}
65impl RegisterBlock {
66 #[doc = "0xff0 - PrimeCell identification 3"]
67 #[inline(always)]
68 pub fn pcell_id_3(&self) -> &crate::Reg<pcell_id_3::PCELL_ID_3_SPEC> {
69 unsafe {
70 &*(((self as *const Self) as *const u8).add(4080usize)
71 as *const crate::Reg<pcell_id_3::PCELL_ID_3_SPEC>)
72 }
73 }
74 #[doc = "0xff0 - PrimeCell identification 2"]
75 #[inline(always)]
76 pub fn pcell_id_2(&self) -> &crate::Reg<pcell_id_2::PCELL_ID_2_SPEC> {
77 unsafe {
78 &*(((self as *const Self) as *const u8).add(4080usize)
79 as *const crate::Reg<pcell_id_2::PCELL_ID_2_SPEC>)
80 }
81 }
82 #[doc = "0xff0 - PrimeCell identification 1"]
83 #[inline(always)]
84 pub fn pcell_id_1(&self) -> &crate::Reg<pcell_id_1::PCELL_ID_1_SPEC> {
85 unsafe {
86 &*(((self as *const Self) as *const u8).add(4080usize)
87 as *const crate::Reg<pcell_id_1::PCELL_ID_1_SPEC>)
88 }
89 }
90 #[doc = "0xff0 - PrimeCell identification 0"]
91 #[inline(always)]
92 pub fn pcell_id_0(&self) -> &crate::Reg<pcell_id_0::PCELL_ID_0_SPEC> {
93 unsafe {
94 &*(((self as *const Self) as *const u8).add(4080usize)
95 as *const crate::Reg<pcell_id_0::PCELL_ID_0_SPEC>)
96 }
97 }
98}
99#[doc = "DMA_STATUS register accessor: an alias for `Reg<DMA_STATUS_SPEC>`"]
100pub type DMA_STATUS = crate::Reg<dma_status::DMA_STATUS_SPEC>;
101#[doc = "DMA Status register"]
102pub mod dma_status;
103#[doc = "DMA_CFG register accessor: an alias for `Reg<DMA_CFG_SPEC>`"]
104pub type DMA_CFG = crate::Reg<dma_cfg::DMA_CFG_SPEC>;
105#[doc = "DMA configuration register"]
106pub mod dma_cfg;
107#[doc = "CTRL_BASE_PTR register accessor: an alias for `Reg<CTRL_BASE_PTR_SPEC>`"]
108pub type CTRL_BASE_PTR = crate::Reg<ctrl_base_ptr::CTRL_BASE_PTR_SPEC>;
109#[doc = "Control the pointer to the base address of the primary data structure"]
110pub mod ctrl_base_ptr;
111#[doc = "ALT_CTRL_BASE_PTR register accessor: an alias for `Reg<ALT_CTRL_BASE_PTR_SPEC>`"]
112pub type ALT_CTRL_BASE_PTR =
113 crate::Reg<alt_ctrl_base_ptr::ALT_CTRL_BASE_PTR_SPEC>;
114#[doc = "Base address of the alternate data structure."]
115pub mod alt_ctrl_base_ptr;
116#[doc = "DMA_WAITONREQ_STATUS register accessor: an alias for `Reg<DMA_WAITONREQ_STATUS_SPEC>`"]
117pub type DMA_WAITONREQ_STATUS =
118 crate::Reg<dma_waitonreq_status::DMA_WAITONREQ_STATUS_SPEC>;
119#[doc = "Channel wait on request status"]
120pub mod dma_waitonreq_status;
121#[doc = "CHNL_SW_REQ register accessor: an alias for `Reg<CHNL_SW_REQ_SPEC>`"]
122pub type CHNL_SW_REQ = crate::Reg<chnl_sw_req::CHNL_SW_REQ_SPEC>;
123#[doc = "Registers to generate a software DMA request in one of the 16 DMA channels"]
124pub mod chnl_sw_req;
125#[doc = "CHNL_USE_BURST_SET register accessor: an alias for `Reg<CHNL_USE_BURST_SET_SPEC>`"]
126pub type CHNL_USE_BURST_SET =
127 crate::Reg<chnl_use_burst_set::CHNL_USE_BURST_SET_SPEC>;
128#[doc = "Returns the useburst status, or disables dma_sreq\\[Channel\\]
129from generating DMA requests"]
130pub mod chnl_use_burst_set;
131#[doc = "CHNL_USEBURST_SET register accessor: an alias for `Reg<CHNL_USEBURST_SET_SPEC>`"]
132pub type CHNL_USEBURST_SET =
133 crate::Reg<chnl_useburst_set::CHNL_USEBURST_SET_SPEC>;
134#[doc = "Set the appropriate bit to enable dma_sreq\\[Channel\\]
135to generate requests."]
136pub mod chnl_useburst_set;
137#[doc = "CHNL_REQ_MASK_SET register accessor: an alias for `Reg<CHNL_REQ_MASK_SET_SPEC>`"]
138pub type CHNL_REQ_MASK_SET =
139 crate::Reg<chnl_req_mask_set::CHNL_REQ_MASK_SET_SPEC>;
140#[doc = "Returns the request mask status of dma_req\\[\\]
141and dma_sreq\\[\\], or disables the corresponding channel from generating DMA requests."]
142pub mod chnl_req_mask_set;
143#[doc = "CHNL_REQ_MASK_CLR register accessor: an alias for `Reg<CHNL_REQ_MASK_CLR_SPEC>`"]
144pub type CHNL_REQ_MASK_CLR =
145 crate::Reg<chnl_req_mask_clr::CHNL_REQ_MASK_CLR_SPEC>;
146#[doc = "Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req\\[C\\]
147and dma_sreq\\[C\\]."]
148pub mod chnl_req_mask_clr;
149#[doc = "CHNL_ENABLE_SET register accessor: an alias for `Reg<CHNL_ENABLE_SET_SPEC>`"]
150pub type CHNL_ENABLE_SET = crate::Reg<chnl_enable_set::CHNL_ENABLE_SET_SPEC>;
151#[doc = "Returns the enable status of the channels, or enables the corresponding channels."]
152pub mod chnl_enable_set;
153#[doc = "CHNL_ENABLE_CLR register accessor: an alias for `Reg<CHNL_ENABLE_CLR_SPEC>`"]
154pub type CHNL_ENABLE_CLR = crate::Reg<chnl_enable_clr::CHNL_ENABLE_CLR_SPEC>;
155#[doc = "Set the appropriate bit to disable the corresponding DMA channel."]
156pub mod chnl_enable_clr;
157#[doc = "CHNL_PRI_ALT_SET register accessor: an alias for `Reg<CHNL_PRI_ALT_SET_SPEC>`"]
158pub type CHNL_PRI_ALT_SET = crate::Reg<chnl_pri_alt_set::CHNL_PRI_ALT_SET_SPEC>;
159#[doc = "Returns the channel control data structure status, or selects the alternate data structure for the corresponding DMA channel."]
160pub mod chnl_pri_alt_set;
161#[doc = "CHNL_PRI_ALT_CLR register accessor: an alias for `Reg<CHNL_PRI_ALT_CLR_SPEC>`"]
162pub type CHNL_PRI_ALT_CLR = crate::Reg<chnl_pri_alt_clr::CHNL_PRI_ALT_CLR_SPEC>;
163#[doc = "Set the appropriate bit to select the primary data structure for the corresponding DMA channel."]
164pub mod chnl_pri_alt_clr;
165#[doc = "CHNL_PRIORITY_SET register accessor: an alias for `Reg<CHNL_PRIORITY_SET_SPEC>`"]
166pub type CHNL_PRIORITY_SET =
167 crate::Reg<chnl_priority_set::CHNL_PRIORITY_SET_SPEC>;
168#[doc = "Returns the channel priority mask status, or sets the channel priority to high."]
169pub mod chnl_priority_set;
170#[doc = "CHNL_PRIORITY_CLEAR register accessor: an alias for `Reg<CHNL_PRIORITY_CLEAR_SPEC>`"]
171pub type CHNL_PRIORITY_CLEAR =
172 crate::Reg<chnl_priority_clear::CHNL_PRIORITY_CLEAR_SPEC>;
173#[doc = "Set the appropriate bit to select the default priority level for the specified DMA channel."]
174pub mod chnl_priority_clear;
175#[doc = "ERR_CLR register accessor: an alias for `Reg<ERR_CLR_SPEC>`"]
176pub type ERR_CLR = crate::Reg<err_clr::ERR_CLR_SPEC>;
177#[doc = "Returns the status of dma_err, or sets the signal LOW."]
178pub mod err_clr;
179#[doc = "PERIPH_ID_4 register accessor: an alias for `Reg<PERIPH_ID_4_SPEC>`"]
180pub type PERIPH_ID_4 = crate::Reg<periph_id_4::PERIPH_ID_4_SPEC>;
181#[doc = "Peripheral identification 4"]
182pub mod periph_id_4;
183#[doc = "PERIPH_ID_0 register accessor: an alias for `Reg<PERIPH_ID_0_SPEC>`"]
184pub type PERIPH_ID_0 = crate::Reg<periph_id_0::PERIPH_ID_0_SPEC>;
185#[doc = "Peripheral identification 0"]
186pub mod periph_id_0;
187#[doc = "PERIPH_ID_1 register accessor: an alias for `Reg<PERIPH_ID_1_SPEC>`"]
188pub type PERIPH_ID_1 = crate::Reg<periph_id_1::PERIPH_ID_1_SPEC>;
189#[doc = "Peripheral identification 1"]
190pub mod periph_id_1;
191#[doc = "PERIPH_ID_2 register accessor: an alias for `Reg<PERIPH_ID_2_SPEC>`"]
192pub type PERIPH_ID_2 = crate::Reg<periph_id_2::PERIPH_ID_2_SPEC>;
193#[doc = "Peripheral identification 2"]
194pub mod periph_id_2;
195#[doc = "PERIPH_ID_3 register accessor: an alias for `Reg<PERIPH_ID_3_SPEC>`"]
196pub type PERIPH_ID_3 = crate::Reg<periph_id_3::PERIPH_ID_3_SPEC>;
197#[doc = "Peripheral identification 3"]
198pub mod periph_id_3;
199#[doc = "PCELL_ID_0 register accessor: an alias for `Reg<PCELL_ID_0_SPEC>`"]
200pub type PCELL_ID_0 = crate::Reg<pcell_id_0::PCELL_ID_0_SPEC>;
201#[doc = "PrimeCell identification 0"]
202pub mod pcell_id_0;
203#[doc = "PCELL_ID_1 register accessor: an alias for `Reg<PCELL_ID_1_SPEC>`"]
204pub type PCELL_ID_1 = crate::Reg<pcell_id_1::PCELL_ID_1_SPEC>;
205#[doc = "PrimeCell identification 1"]
206pub mod pcell_id_1;
207#[doc = "PCELL_ID_2 register accessor: an alias for `Reg<PCELL_ID_2_SPEC>`"]
208pub type PCELL_ID_2 = crate::Reg<pcell_id_2::PCELL_ID_2_SPEC>;
209#[doc = "PrimeCell identification 2"]
210pub mod pcell_id_2;
211#[doc = "PCELL_ID_3 register accessor: an alias for `Reg<PCELL_ID_3_SPEC>`"]
212pub type PCELL_ID_3 = crate::Reg<pcell_id_3::PCELL_ID_3_SPEC>;
213#[doc = "PrimeCell identification 3"]
214pub mod pcell_id_3;