pub struct Cache { /* private fields */ }Implementations§
Source§impl Cache
impl Cache
Sourcepub const fn cache_ctrl2_reg(&self) -> &'static Reg<CacheCtrl2Reg_SPEC, RW>
pub const fn cache_ctrl2_reg(&self) -> &'static Reg<CacheCtrl2Reg_SPEC, RW>
Cache control register 2 (only Word (32-bits) access supported).
Sourcepub const fn cache_flash_reg(&self) -> &'static Reg<CacheFlashReg_SPEC, RW>
pub const fn cache_flash_reg(&self) -> &'static Reg<CacheFlashReg_SPEC, RW>
Cache QSPI Flash program size and base address register (only Word (32-bits) access supported).
Sourcepub const fn cache_mrm_ctrl_reg(&self) -> &'static Reg<CacheMrmCtrlReg_SPEC, RW>
pub const fn cache_mrm_ctrl_reg(&self) -> &'static Reg<CacheMrmCtrlReg_SPEC, RW>
Cache MRM (Miss Rate Monitor) CONTROL register (only Word (32-bits) access supported).
Sourcepub const fn cache_mrm_hits1ws_reg(
&self,
) -> &'static Reg<CacheMrmHits1WsReg_SPEC, RW>
pub const fn cache_mrm_hits1ws_reg( &self, ) -> &'static Reg<CacheMrmHits1WsReg_SPEC, RW>
Cache MRM (Miss Rate Monitor) HITS with 1 Wait State register (only Word (32-bits) access supported).
Sourcepub const fn cache_mrm_hits_reg(&self) -> &'static Reg<CacheMrmHitsReg_SPEC, RW>
pub const fn cache_mrm_hits_reg(&self) -> &'static Reg<CacheMrmHitsReg_SPEC, RW>
Cache MRM (Miss Rate Monitor) HITS register (only Word (32-bits) access supported).
Sourcepub const fn cache_mrm_hits_thres_reg(
&self,
) -> &'static Reg<CacheMrmHitsThresReg_SPEC, RW>
pub const fn cache_mrm_hits_thres_reg( &self, ) -> &'static Reg<CacheMrmHitsThresReg_SPEC, RW>
Cache MRM (Miss Rate Monitor) HITS THRESHOLD register (only Word (32-bits) access supported).
Sourcepub const fn cache_mrm_misses_reg(
&self,
) -> &'static Reg<CacheMrmMissesReg_SPEC, RW>
pub const fn cache_mrm_misses_reg( &self, ) -> &'static Reg<CacheMrmMissesReg_SPEC, RW>
Cache MRM (Miss Rate Monitor) MISSES register (only Word (32-bits) access supported).
Sourcepub const fn cache_mrm_misses_thres_reg(
&self,
) -> &'static Reg<CacheMrmMissesThresReg_SPEC, RW>
pub const fn cache_mrm_misses_thres_reg( &self, ) -> &'static Reg<CacheMrmMissesThresReg_SPEC, RW>
Cache MRM (Miss Rate Monitor) THRESHOLD register (only Word (32-bits) access supported).
Sourcepub const fn cache_mrm_tint_reg(&self) -> &'static Reg<CacheMrmTintReg_SPEC, RW>
pub const fn cache_mrm_tint_reg(&self) -> &'static Reg<CacheMrmTintReg_SPEC, RW>
Cache MRM (Miss Rate Monitor) TIME INTERVAL register (only Word (32-bits) access supported).
Sourcepub const fn swd_reset_reg(&self) -> &'static Reg<SwdResetReg_SPEC, RW>
pub const fn swd_reset_reg(&self) -> &'static Reg<SwdResetReg_SPEC, RW>
SWD HW reset control register (only Word (32-bits) access supported).
Trait Implementations§
impl Copy for Cache
impl Eq for Cache
impl Send for Cache
CACHE registers