da1470x_pac/
lib.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:45:52 +0000
19#![cfg_attr(not(feature = "tracing"), no_std)]
20#![allow(non_camel_case_types)]
21#![doc = "D2798AA"]
22pub mod common;
23pub use common::*;
24
25#[cfg(feature = "tracing")]
26pub mod reg_name;
27#[cfg(feature = "tracing")]
28pub mod tracing;
29
30#[cfg(feature = "aes_hash")]
31pub mod aes_hash;
32#[cfg(feature = "anamisc_bif")]
33pub mod anamisc_bif;
34#[cfg(feature = "cache")]
35pub mod cache;
36#[cfg(feature = "charger")]
37pub mod charger;
38#[cfg(feature = "chg_det")]
39pub mod chg_det;
40#[cfg(feature = "crg_aud")]
41pub mod crg_aud;
42#[cfg(feature = "crg_ctrl")]
43pub mod crg_ctrl;
44#[cfg(feature = "crg_gpu")]
45pub mod crg_gpu;
46#[cfg(feature = "crg_snc")]
47pub mod crg_snc;
48#[cfg(feature = "crg_sys")]
49pub mod crg_sys;
50#[cfg(feature = "crg_top")]
51pub mod crg_top;
52#[cfg(feature = "crg_vsys")]
53pub mod crg_vsys;
54#[cfg(feature = "crg_xtal")]
55pub mod crg_xtal;
56#[cfg(feature = "dcache")]
57pub mod dcache;
58#[cfg(feature = "dcdc")]
59pub mod dcdc;
60#[cfg(feature = "dcdc_boost")]
61pub mod dcdc_boost;
62#[cfg(feature = "dma")]
63pub mod dma;
64#[cfg(feature = "dsi2")]
65pub mod dsi2;
66#[cfg(feature = "dsidphy_reg")]
67pub mod dsidphy_reg;
68#[cfg(feature = "emmc")]
69pub mod emmc;
70#[cfg(feature = "gpadc")]
71pub mod gpadc;
72#[cfg(feature = "gpio")]
73pub mod gpio;
74#[cfg(feature = "gpreg")]
75pub mod gpreg;
76#[cfg(feature = "gpu_core")]
77pub mod gpu_core;
78#[cfg(feature = "gpu_reg")]
79pub mod gpu_reg;
80#[cfg(feature = "i2c")]
81pub mod i2c;
82#[cfg(feature = "i2c2")]
83pub mod i2c2;
84#[cfg(feature = "i2c3")]
85pub mod i2c3;
86#[cfg(feature = "i3c")]
87pub mod i3c;
88#[cfg(feature = "lcdc")]
89pub mod lcdc;
90#[cfg(feature = "memctrl")]
91pub mod memctrl;
92#[cfg(feature = "oqspif")]
93pub mod oqspif;
94
95#[cfg(feature = "aes_hash")]
96#[derive(Copy, Clone, Eq, PartialEq)]
97pub struct AesHash {
98    ptr: *mut u8,
99}
100#[cfg(feature = "aes_hash")]
101pub const AES_HASH: self::AesHash = self::AesHash {
102    ptr: 0x30040000u32 as _,
103};
104#[cfg(feature = "anamisc_bif")]
105#[derive(Copy, Clone, Eq, PartialEq)]
106pub struct AnamiscBif {
107    ptr: *mut u8,
108}
109#[cfg(feature = "anamisc_bif")]
110pub const ANAMISC_BIF: self::AnamiscBif = self::AnamiscBif {
111    ptr: 0x50050600u32 as _,
112};
113#[cfg(feature = "cache")]
114#[derive(Copy, Clone, Eq, PartialEq)]
115pub struct Cache {
116    ptr: *mut u8,
117}
118#[cfg(feature = "cache")]
119pub const CACHE: self::Cache = self::Cache {
120    ptr: 0x100c0000u32 as _,
121};
122#[cfg(feature = "charger")]
123#[derive(Copy, Clone, Eq, PartialEq)]
124pub struct Charger {
125    ptr: *mut u8,
126}
127#[cfg(feature = "charger")]
128pub const CHARGER: self::Charger = self::Charger {
129    ptr: 0x51000600u32 as _,
130};
131#[cfg(feature = "chg_det")]
132#[derive(Copy, Clone, Eq, PartialEq)]
133pub struct ChgDet {
134    ptr: *mut u8,
135}
136#[cfg(feature = "chg_det")]
137pub const CHG_DET: self::ChgDet = self::ChgDet {
138    ptr: 0x50040300u32 as _,
139};
140#[cfg(feature = "crg_aud")]
141#[derive(Copy, Clone, Eq, PartialEq)]
142pub struct CrgAud {
143    ptr: *mut u8,
144}
145#[cfg(feature = "crg_aud")]
146pub const CRG_AUD: self::CrgAud = self::CrgAud {
147    ptr: 0x50030000u32 as _,
148};
149#[cfg(feature = "crg_ctrl")]
150#[derive(Copy, Clone, Eq, PartialEq)]
151pub struct CrgCtrl {
152    ptr: *mut u8,
153}
154#[cfg(feature = "crg_ctrl")]
155pub const CRG_CTRL: self::CrgCtrl = self::CrgCtrl {
156    ptr: 0x50060000u32 as _,
157};
158#[cfg(feature = "crg_gpu")]
159#[derive(Copy, Clone, Eq, PartialEq)]
160pub struct CrgGpu {
161    ptr: *mut u8,
162}
163#[cfg(feature = "crg_gpu")]
164pub const CRG_GPU: self::CrgGpu = self::CrgGpu {
165    ptr: 0x51001000u32 as _,
166};
167#[cfg(feature = "crg_snc")]
168#[derive(Copy, Clone, Eq, PartialEq)]
169pub struct CrgSnc {
170    ptr: *mut u8,
171}
172#[cfg(feature = "crg_snc")]
173pub const CRG_SNC: self::CrgSnc = self::CrgSnc {
174    ptr: 0x50020900u32 as _,
175};
176#[cfg(feature = "crg_sys")]
177#[derive(Copy, Clone, Eq, PartialEq)]
178pub struct CrgSys {
179    ptr: *mut u8,
180}
181#[cfg(feature = "crg_sys")]
182pub const CRG_SYS: self::CrgSys = self::CrgSys {
183    ptr: 0x50040400u32 as _,
184};
185#[cfg(feature = "crg_top")]
186#[derive(Copy, Clone, Eq, PartialEq)]
187pub struct CrgTop {
188    ptr: *mut u8,
189}
190#[cfg(feature = "crg_top")]
191pub const CRG_TOP: self::CrgTop = self::CrgTop {
192    ptr: 0x50000000u32 as _,
193};
194#[cfg(feature = "crg_vsys")]
195#[derive(Copy, Clone, Eq, PartialEq)]
196pub struct CrgVsys {
197    ptr: *mut u8,
198}
199#[cfg(feature = "crg_vsys")]
200pub const CRG_VSYS: self::CrgVsys = self::CrgVsys {
201    ptr: 0x50000b00u32 as _,
202};
203#[cfg(feature = "crg_xtal")]
204#[derive(Copy, Clone, Eq, PartialEq)]
205pub struct CrgXtal {
206    ptr: *mut u8,
207}
208#[cfg(feature = "crg_xtal")]
209pub const CRG_XTAL: self::CrgXtal = self::CrgXtal {
210    ptr: 0x50050400u32 as _,
211};
212#[cfg(feature = "dcache")]
213#[derive(Copy, Clone, Eq, PartialEq)]
214pub struct Dcache {
215    ptr: *mut u8,
216}
217#[cfg(feature = "dcache")]
218pub const DCACHE: self::Dcache = self::Dcache {
219    ptr: 0x30100000u32 as _,
220};
221#[cfg(feature = "dcdc")]
222#[derive(Copy, Clone, Eq, PartialEq)]
223pub struct Dcdc {
224    ptr: *mut u8,
225}
226#[cfg(feature = "dcdc")]
227pub const DCDC: self::Dcdc = self::Dcdc {
228    ptr: 0x50000300u32 as _,
229};
230#[cfg(feature = "dcdc_boost")]
231#[derive(Copy, Clone, Eq, PartialEq)]
232pub struct DcdcBoost {
233    ptr: *mut u8,
234}
235#[cfg(feature = "dcdc_boost")]
236pub const DCDC_BOOST: self::DcdcBoost = self::DcdcBoost {
237    ptr: 0x50000500u32 as _,
238};
239#[cfg(feature = "dma")]
240#[derive(Copy, Clone, Eq, PartialEq)]
241pub struct Dma {
242    ptr: *mut u8,
243}
244#[cfg(feature = "dma")]
245pub const DMA: self::Dma = self::Dma {
246    ptr: 0x51000400u32 as _,
247};
248#[cfg(feature = "dsi2")]
249#[derive(Copy, Clone, Eq, PartialEq)]
250pub struct Dsi2 {
251    ptr: *mut u8,
252}
253#[cfg(feature = "dsi2")]
254pub const DSI2: self::Dsi2 = self::Dsi2 {
255    ptr: 0x51001300u32 as _,
256};
257#[cfg(feature = "dsidphy_reg")]
258#[derive(Copy, Clone, Eq, PartialEq)]
259pub struct DsidphyReg {
260    ptr: *mut u8,
261}
262#[cfg(feature = "dsidphy_reg")]
263pub const DSIDPHY_REG: self::DsidphyReg = self::DsidphyReg {
264    ptr: 0x51001500u32 as _,
265};
266#[cfg(feature = "emmc")]
267#[derive(Copy, Clone, Eq, PartialEq)]
268pub struct Emmc {
269    ptr: *mut u8,
270}
271#[cfg(feature = "emmc")]
272pub const EMMC: self::Emmc = self::Emmc {
273    ptr: 0x30058000u32 as _,
274};
275#[cfg(feature = "gpadc")]
276#[derive(Copy, Clone, Eq, PartialEq)]
277pub struct Gpadc {
278    ptr: *mut u8,
279}
280#[cfg(feature = "gpadc")]
281pub const GPADC: self::Gpadc = self::Gpadc {
282    ptr: 0x50020800u32 as _,
283};
284#[cfg(feature = "gpio")]
285#[derive(Copy, Clone, Eq, PartialEq)]
286pub struct Gpio {
287    ptr: *mut u8,
288}
289#[cfg(feature = "gpio")]
290pub const GPIO: self::Gpio = self::Gpio {
291    ptr: 0x50050100u32 as _,
292};
293#[cfg(feature = "gpreg")]
294#[derive(Copy, Clone, Eq, PartialEq)]
295pub struct Gpreg {
296    ptr: *mut u8,
297}
298#[cfg(feature = "gpreg")]
299pub const GPREG: self::Gpreg = self::Gpreg {
300    ptr: 0x50040100u32 as _,
301};
302#[cfg(feature = "gpu_core")]
303#[derive(Copy, Clone, Eq, PartialEq)]
304pub struct GpuCore {
305    ptr: *mut u8,
306}
307#[cfg(feature = "gpu_core")]
308pub const GPU_CORE: self::GpuCore = self::GpuCore {
309    ptr: 0x51001200u32 as _,
310};
311#[cfg(feature = "gpu_reg")]
312#[derive(Copy, Clone, Eq, PartialEq)]
313pub struct GpuReg {
314    ptr: *mut u8,
315}
316#[cfg(feature = "gpu_reg")]
317pub const GPU_REG: self::GpuReg = self::GpuReg {
318    ptr: 0x51001100u32 as _,
319};
320#[cfg(feature = "i2c")]
321#[derive(Copy, Clone, Eq, PartialEq)]
322pub struct I2C {
323    ptr: *mut u8,
324}
325#[cfg(feature = "i2c")]
326pub const I2C: self::I2C = self::I2C {
327    ptr: 0x50020600u32 as _,
328};
329#[cfg(feature = "i2c2")]
330#[derive(Copy, Clone, Eq, PartialEq)]
331pub struct I2C2 {
332    ptr: *mut u8,
333}
334#[cfg(feature = "i2c2")]
335pub const I2C2: self::I2C2 = self::I2C2 {
336    ptr: 0x50020700u32 as _,
337};
338#[cfg(feature = "i2c3")]
339#[derive(Copy, Clone, Eq, PartialEq)]
340pub struct I2C3 {
341    ptr: *mut u8,
342}
343#[cfg(feature = "i2c3")]
344pub const I2C3: self::I2C3 = self::I2C3 {
345    ptr: 0x50020500u32 as _,
346};
347#[cfg(feature = "i3c")]
348#[derive(Copy, Clone, Eq, PartialEq)]
349pub struct I3C {
350    ptr: *mut u8,
351}
352#[cfg(feature = "i3c")]
353pub const I3C: self::I3C = self::I3C {
354    ptr: 0x50020c00u32 as _,
355};
356#[cfg(feature = "lcdc")]
357#[derive(Copy, Clone, Eq, PartialEq)]
358pub struct Lcdc {
359    ptr: *mut u8,
360}
361#[cfg(feature = "lcdc")]
362pub const LCDC: self::Lcdc = self::Lcdc {
363    ptr: 0x30030000u32 as _,
364};
365#[cfg(feature = "memctrl")]
366#[derive(Copy, Clone, Eq, PartialEq)]
367pub struct Memctrl {
368    ptr: *mut u8,
369}
370#[cfg(feature = "memctrl")]
371pub const MEMCTRL: self::Memctrl = self::Memctrl {
372    ptr: 0x50050000u32 as _,
373};
374#[cfg(feature = "oqspif")]
375#[derive(Copy, Clone, Eq, PartialEq)]
376pub struct Oqspif {
377    ptr: *mut u8,
378}
379#[cfg(feature = "oqspif")]
380pub const OQSPIF: self::Oqspif = self::Oqspif {
381    ptr: 0x36000000u32 as _,
382};
383
384pub use cortex_m::peripheral::Peripherals as CorePeripherals;
385pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
386#[doc = "Number available in the NVIC for configuring priority"]
387pub const NVIC_PRIO_BITS: u8 = 4;
388#[doc(hidden)]
389pub union Vector {
390    _handler: unsafe extern "C" fn(),
391    _reserved: u32,
392}
393#[cfg(feature = "rt")]
394pub use self::Interrupt as interrupt;
395#[cfg(feature = "rt")]
396pub use cortex_m_rt::interrupt;
397#[cfg(feature = "rt")]
398pub mod interrupt_handlers {
399    unsafe extern "C" {
400        pub fn CMAC2SYS();
401        pub fn SNC2SYS();
402        pub fn M33_CACHE_MRM();
403        pub fn PDC_M33();
404        pub fn KEY_WKUP_GPIO();
405        pub fn VBUS();
406        pub fn CHARGER_STATE();
407        pub fn CHARGER_ERROR();
408        pub fn DCDC_BOOST();
409        pub fn PLL48_LOCK();
410        pub fn CRYPTO();
411        pub fn PLL_LOCK();
412        pub fn XTAL32M_RDY();
413        pub fn RFDIAG();
414        pub fn GPIO_P0();
415        pub fn GPIO_P1();
416        pub fn GPIO_P2();
417        pub fn TIMER();
418        pub fn TIMER2();
419        pub fn TIMER3();
420        pub fn TIMER4();
421        pub fn TIMER5();
422        pub fn TIMER6();
423        pub fn RTC();
424        pub fn RTC_EVENT();
425        pub fn CAPTIMER();
426        pub fn ADC();
427        pub fn ADC2();
428        pub fn DMA();
429        pub fn UART();
430        pub fn UART2();
431        pub fn UART3();
432        pub fn SPI();
433        pub fn SPI2();
434        pub fn SPI3();
435        pub fn I2C();
436        pub fn I2C2();
437        pub fn I2C3();
438        pub fn I3C();
439        pub fn USB();
440        pub fn PCM();
441        pub fn SRC_IN();
442        pub fn SRC_OUT();
443        pub fn SRC2_IN();
444        pub fn SRC2_OUT();
445        pub fn VAD();
446        pub fn EMMC();
447        pub fn SDIO();
448        pub fn GPU();
449        pub fn LCD();
450        pub fn DSI();
451        pub fn CHARGER_DET();
452        pub fn DCACHE_MRM();
453        pub fn CLK_CALIBRATION();
454        pub fn VSYS_GEN();
455        pub fn RESERVED55();
456    }
457}
458#[cfg(feature = "rt")]
459#[doc(hidden)]
460#[unsafe(link_section = ".vector_table.interrupts")]
461#[unsafe(no_mangle)]
462pub static __INTERRUPTS: [Vector; 56] = [
463    Vector {
464        _handler: interrupt_handlers::CMAC2SYS,
465    },
466    Vector {
467        _handler: interrupt_handlers::SNC2SYS,
468    },
469    Vector {
470        _handler: interrupt_handlers::M33_CACHE_MRM,
471    },
472    Vector {
473        _handler: interrupt_handlers::PDC_M33,
474    },
475    Vector {
476        _handler: interrupt_handlers::KEY_WKUP_GPIO,
477    },
478    Vector {
479        _handler: interrupt_handlers::VBUS,
480    },
481    Vector {
482        _handler: interrupt_handlers::CHARGER_STATE,
483    },
484    Vector {
485        _handler: interrupt_handlers::CHARGER_ERROR,
486    },
487    Vector {
488        _handler: interrupt_handlers::DCDC_BOOST,
489    },
490    Vector {
491        _handler: interrupt_handlers::PLL48_LOCK,
492    },
493    Vector {
494        _handler: interrupt_handlers::CRYPTO,
495    },
496    Vector {
497        _handler: interrupt_handlers::PLL_LOCK,
498    },
499    Vector {
500        _handler: interrupt_handlers::XTAL32M_RDY,
501    },
502    Vector {
503        _handler: interrupt_handlers::RFDIAG,
504    },
505    Vector {
506        _handler: interrupt_handlers::GPIO_P0,
507    },
508    Vector {
509        _handler: interrupt_handlers::GPIO_P1,
510    },
511    Vector {
512        _handler: interrupt_handlers::GPIO_P2,
513    },
514    Vector {
515        _handler: interrupt_handlers::TIMER,
516    },
517    Vector {
518        _handler: interrupt_handlers::TIMER2,
519    },
520    Vector {
521        _handler: interrupt_handlers::TIMER3,
522    },
523    Vector {
524        _handler: interrupt_handlers::TIMER4,
525    },
526    Vector {
527        _handler: interrupt_handlers::TIMER5,
528    },
529    Vector {
530        _handler: interrupt_handlers::TIMER6,
531    },
532    Vector {
533        _handler: interrupt_handlers::RTC,
534    },
535    Vector {
536        _handler: interrupt_handlers::RTC_EVENT,
537    },
538    Vector {
539        _handler: interrupt_handlers::CAPTIMER,
540    },
541    Vector {
542        _handler: interrupt_handlers::ADC,
543    },
544    Vector {
545        _handler: interrupt_handlers::ADC2,
546    },
547    Vector {
548        _handler: interrupt_handlers::DMA,
549    },
550    Vector {
551        _handler: interrupt_handlers::UART,
552    },
553    Vector {
554        _handler: interrupt_handlers::UART2,
555    },
556    Vector {
557        _handler: interrupt_handlers::UART3,
558    },
559    Vector {
560        _handler: interrupt_handlers::SPI,
561    },
562    Vector {
563        _handler: interrupt_handlers::SPI2,
564    },
565    Vector {
566        _handler: interrupt_handlers::SPI3,
567    },
568    Vector {
569        _handler: interrupt_handlers::I2C,
570    },
571    Vector {
572        _handler: interrupt_handlers::I2C2,
573    },
574    Vector {
575        _handler: interrupt_handlers::I2C3,
576    },
577    Vector {
578        _handler: interrupt_handlers::I3C,
579    },
580    Vector {
581        _handler: interrupt_handlers::USB,
582    },
583    Vector {
584        _handler: interrupt_handlers::PCM,
585    },
586    Vector {
587        _handler: interrupt_handlers::SRC_IN,
588    },
589    Vector {
590        _handler: interrupt_handlers::SRC_OUT,
591    },
592    Vector {
593        _handler: interrupt_handlers::SRC2_IN,
594    },
595    Vector {
596        _handler: interrupt_handlers::SRC2_OUT,
597    },
598    Vector {
599        _handler: interrupt_handlers::VAD,
600    },
601    Vector {
602        _handler: interrupt_handlers::EMMC,
603    },
604    Vector {
605        _handler: interrupt_handlers::SDIO,
606    },
607    Vector {
608        _handler: interrupt_handlers::GPU,
609    },
610    Vector {
611        _handler: interrupt_handlers::LCD,
612    },
613    Vector {
614        _handler: interrupt_handlers::DSI,
615    },
616    Vector {
617        _handler: interrupt_handlers::CHARGER_DET,
618    },
619    Vector {
620        _handler: interrupt_handlers::DCACHE_MRM,
621    },
622    Vector {
623        _handler: interrupt_handlers::CLK_CALIBRATION,
624    },
625    Vector {
626        _handler: interrupt_handlers::VSYS_GEN,
627    },
628    Vector {
629        _handler: interrupt_handlers::RESERVED55,
630    },
631];
632#[doc = "Enumeration of all the interrupts."]
633#[derive(Copy, Clone, Debug, PartialEq, Eq)]
634#[repr(u16)]
635pub enum Interrupt {
636    #[doc = "CMAC and mailbox interrupt request."]
637    CMAC2SYS = 0,
638
639    #[doc = "SNC M0+ interrupt to Cortex M33."]
640    SNC2SYS = 1,
641
642    #[doc = "CM33 Cache Miss Rate Monitor interrupt request."]
643    M33_CACHE_MRM = 2,
644
645    #[doc = "Wakeup IRQ from PDC to CM33."]
646    PDC_M33 = 3,
647
648    #[doc = "Debounced button press interrupt request."]
649    KEY_WKUP_GPIO = 4,
650
651    #[doc = "VBUS presence interrupt request."]
652    VBUS = 5,
653
654    #[doc = "Charger State interrupt request."]
655    CHARGER_STATE = 6,
656
657    #[doc = "Charger Error interrupt request."]
658    CHARGER_ERROR = 7,
659
660    #[doc = "DCDC boost controller interrupt request."]
661    DCDC_BOOST = 8,
662
663    #[doc = "PLL48 lock interrupt request. Indicates that the PLL48 is locked at 48MHz."]
664    PLL48_LOCK = 9,
665
666    #[doc = "Crypto interrupt request."]
667    CRYPTO = 10,
668
669    #[doc = "PLL lock interrupt request. Indicates that PLL is locked at 160MHz."]
670    PLL_LOCK = 11,
671
672    #[doc = "XTAL32M trimmed and ready interrupt request."]
673    XTAL32M_RDY = 12,
674
675    #[doc = "Baseband or Radio Diagnostics interrupt request."]
676    RFDIAG = 13,
677
678    #[doc = "GPIO port 0 toggle interrupt request."]
679    GPIO_P0 = 14,
680
681    #[doc = "GPIO port 1 toggle interrupt request."]
682    GPIO_P1 = 15,
683
684    #[doc = "GPIO port 2 toggle interrupt request."]
685    GPIO_P2 = 16,
686
687    #[doc = "TIMER interrupt request."]
688    TIMER = 17,
689
690    #[doc = "TIMER2 interrupt request."]
691    TIMER2 = 18,
692
693    #[doc = "TIMER3 interrupt request."]
694    TIMER3 = 19,
695
696    #[doc = "TIMER4 interrupt request."]
697    TIMER4 = 20,
698
699    #[doc = "TIMER5 interrupt request."]
700    TIMER5 = 21,
701
702    #[doc = "TIMER6 interrupt request."]
703    TIMER6 = 22,
704
705    #[doc = "RTC interrupt request."]
706    RTC = 23,
707
708    #[doc = "RTC event interrupt request."]
709    RTC_EVENT = 24,
710
711    #[doc = "GPIO triggered Timer Capture interrupt request."]
712    CAPTIMER = 25,
713
714    #[doc = "General Purpose Analog-Digital Converter interrupt request."]
715    ADC = 26,
716
717    #[doc = "Application Analog-Digital Converter interrupt request."]
718    ADC2 = 27,
719
720    #[doc = "General Purpose DMA interrupt request."]
721    DMA = 28,
722
723    #[doc = "UART interrupt request."]
724    UART = 29,
725
726    #[doc = "UART2 interrupt request."]
727    UART2 = 30,
728
729    #[doc = "UART3 interrupt request."]
730    UART3 = 31,
731
732    #[doc = "SPI interrupt request."]
733    SPI = 32,
734
735    #[doc = "SPI2 interrupt request."]
736    SPI2 = 33,
737
738    #[doc = "SPI3 interrupt request."]
739    SPI3 = 34,
740
741    #[doc = "I2C interrupt request."]
742    I2C = 35,
743
744    #[doc = "I2C2 interrupt request."]
745    I2C2 = 36,
746
747    #[doc = "I2C3 interrupt request."]
748    I2C3 = 37,
749
750    #[doc = "I3C interrupt request."]
751    I3C = 38,
752
753    #[doc = "USB interrupt request."]
754    USB = 39,
755
756    #[doc = "PCM interrupt request."]
757    PCM = 40,
758
759    #[doc = "SRC input interrupt request."]
760    SRC_IN = 41,
761
762    #[doc = "SRC output interrupt request."]
763    SRC_OUT = 42,
764
765    #[doc = "SRC2 input interrupt request."]
766    SRC2_IN = 43,
767
768    #[doc = "SRC2 output interrupt request."]
769    SRC2_OUT = 44,
770
771    #[doc = "VAD interrupt request."]
772    VAD = 45,
773
774    #[doc = "eMMC controller interrupt request."]
775    EMMC = 46,
776
777    #[doc = "SDIO controller interrupt request."]
778    SDIO = 47,
779
780    #[doc = "GPU interrupt request to Cortex M33."]
781    GPU = 48,
782
783    #[doc = "LCD controller interrupt request."]
784    LCD = 49,
785
786    #[doc = "DSI/D-PHY interrupt request."]
787    DSI = 50,
788
789    #[doc = "Charger detection interrupt request."]
790    CHARGER_DET = 51,
791
792    #[doc = "Data cache MRM interrupt request."]
793    DCACHE_MRM = 52,
794
795    #[doc = "Clock calibration interrupt request."]
796    CLK_CALIBRATION = 53,
797
798    #[doc = "VSYS generator interrupt request."]
799    VSYS_GEN = 54,
800
801    #[doc = "SoftWare interrupt request."]
802    RESERVED55 = 55,
803}
804unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
805    #[inline(always)]
806    fn number(self) -> u16 {
807        self as u16
808    }
809}
810#[allow(non_snake_case)]
811/// Required for compatibility with RTIC and other frameworks
812pub struct Peripherals {
813    #[cfg(feature = "aes_hash")]
814    pub AES_HASH: self::AesHash,
815    #[cfg(feature = "anamisc_bif")]
816    pub ANAMISC_BIF: self::AnamiscBif,
817    #[cfg(feature = "cache")]
818    pub CACHE: self::Cache,
819    #[cfg(feature = "charger")]
820    pub CHARGER: self::Charger,
821    #[cfg(feature = "chg_det")]
822    pub CHG_DET: self::ChgDet,
823    #[cfg(feature = "crg_aud")]
824    pub CRG_AUD: self::CrgAud,
825    #[cfg(feature = "crg_ctrl")]
826    pub CRG_CTRL: self::CrgCtrl,
827    #[cfg(feature = "crg_gpu")]
828    pub CRG_GPU: self::CrgGpu,
829    #[cfg(feature = "crg_snc")]
830    pub CRG_SNC: self::CrgSnc,
831    #[cfg(feature = "crg_sys")]
832    pub CRG_SYS: self::CrgSys,
833    #[cfg(feature = "crg_top")]
834    pub CRG_TOP: self::CrgTop,
835    #[cfg(feature = "crg_vsys")]
836    pub CRG_VSYS: self::CrgVsys,
837    #[cfg(feature = "crg_xtal")]
838    pub CRG_XTAL: self::CrgXtal,
839    #[cfg(feature = "dcache")]
840    pub DCACHE: self::Dcache,
841    #[cfg(feature = "dcdc")]
842    pub DCDC: self::Dcdc,
843    #[cfg(feature = "dcdc_boost")]
844    pub DCDC_BOOST: self::DcdcBoost,
845    #[cfg(feature = "dma")]
846    pub DMA: self::Dma,
847    #[cfg(feature = "dsi2")]
848    pub DSI2: self::Dsi2,
849    #[cfg(feature = "dsidphy_reg")]
850    pub DSIDPHY_REG: self::DsidphyReg,
851    #[cfg(feature = "emmc")]
852    pub EMMC: self::Emmc,
853    #[cfg(feature = "gpadc")]
854    pub GPADC: self::Gpadc,
855    #[cfg(feature = "gpio")]
856    pub GPIO: self::Gpio,
857    #[cfg(feature = "gpreg")]
858    pub GPREG: self::Gpreg,
859    #[cfg(feature = "gpu_core")]
860    pub GPU_CORE: self::GpuCore,
861    #[cfg(feature = "gpu_reg")]
862    pub GPU_REG: self::GpuReg,
863    #[cfg(feature = "i2c")]
864    pub I2C: self::I2C,
865    #[cfg(feature = "i2c2")]
866    pub I2C2: self::I2C2,
867    #[cfg(feature = "i2c3")]
868    pub I2C3: self::I2C3,
869    #[cfg(feature = "i3c")]
870    pub I3C: self::I3C,
871    #[cfg(feature = "lcdc")]
872    pub LCDC: self::Lcdc,
873    #[cfg(feature = "memctrl")]
874    pub MEMCTRL: self::Memctrl,
875    #[cfg(feature = "oqspif")]
876    pub OQSPIF: self::Oqspif,
877}
878
879impl Peripherals {
880    /// Returns Peripheral struct multiple times
881    /// Required for compatibility with RTIC and other frameworks
882    #[inline]
883    pub fn take() -> Option<Self> {
884        Some(Self::steal())
885    }
886
887    /// Returns Peripheral struct multiple times
888    /// Required for compatibility with RTIC and other frameworks
889    #[inline]
890    pub fn steal() -> Self {
891        Peripherals {
892            #[cfg(feature = "aes_hash")]
893            AES_HASH: crate::AES_HASH,
894            #[cfg(feature = "anamisc_bif")]
895            ANAMISC_BIF: crate::ANAMISC_BIF,
896            #[cfg(feature = "cache")]
897            CACHE: crate::CACHE,
898            #[cfg(feature = "charger")]
899            CHARGER: crate::CHARGER,
900            #[cfg(feature = "chg_det")]
901            CHG_DET: crate::CHG_DET,
902            #[cfg(feature = "crg_aud")]
903            CRG_AUD: crate::CRG_AUD,
904            #[cfg(feature = "crg_ctrl")]
905            CRG_CTRL: crate::CRG_CTRL,
906            #[cfg(feature = "crg_gpu")]
907            CRG_GPU: crate::CRG_GPU,
908            #[cfg(feature = "crg_snc")]
909            CRG_SNC: crate::CRG_SNC,
910            #[cfg(feature = "crg_sys")]
911            CRG_SYS: crate::CRG_SYS,
912            #[cfg(feature = "crg_top")]
913            CRG_TOP: crate::CRG_TOP,
914            #[cfg(feature = "crg_vsys")]
915            CRG_VSYS: crate::CRG_VSYS,
916            #[cfg(feature = "crg_xtal")]
917            CRG_XTAL: crate::CRG_XTAL,
918            #[cfg(feature = "dcache")]
919            DCACHE: crate::DCACHE,
920            #[cfg(feature = "dcdc")]
921            DCDC: crate::DCDC,
922            #[cfg(feature = "dcdc_boost")]
923            DCDC_BOOST: crate::DCDC_BOOST,
924            #[cfg(feature = "dma")]
925            DMA: crate::DMA,
926            #[cfg(feature = "dsi2")]
927            DSI2: crate::DSI2,
928            #[cfg(feature = "dsidphy_reg")]
929            DSIDPHY_REG: crate::DSIDPHY_REG,
930            #[cfg(feature = "emmc")]
931            EMMC: crate::EMMC,
932            #[cfg(feature = "gpadc")]
933            GPADC: crate::GPADC,
934            #[cfg(feature = "gpio")]
935            GPIO: crate::GPIO,
936            #[cfg(feature = "gpreg")]
937            GPREG: crate::GPREG,
938            #[cfg(feature = "gpu_core")]
939            GPU_CORE: crate::GPU_CORE,
940            #[cfg(feature = "gpu_reg")]
941            GPU_REG: crate::GPU_REG,
942            #[cfg(feature = "i2c")]
943            I2C: crate::I2C,
944            #[cfg(feature = "i2c2")]
945            I2C2: crate::I2C2,
946            #[cfg(feature = "i2c3")]
947            I2C3: crate::I2C3,
948            #[cfg(feature = "i3c")]
949            I3C: crate::I3C,
950            #[cfg(feature = "lcdc")]
951            LCDC: crate::LCDC,
952            #[cfg(feature = "memctrl")]
953            MEMCTRL: crate::MEMCTRL,
954            #[cfg(feature = "oqspif")]
955            OQSPIF: crate::OQSPIF,
956        }
957    }
958}
da1470x_pac/lib.rs

da1470x_pac/
lib.rs
