pub type Timer0CtrlReg = RegValueT<Timer0CtrlReg_SPEC>;Expand description
Timer0 control register
Aliased Type§
pub struct Timer0CtrlReg { /* private fields */ }Implementations§
Source§impl Timer0CtrlReg
impl Timer0CtrlReg
Sourcepub fn pwm_mode(self) -> RegisterFieldBool<3, 1, 0, Timer0CtrlReg_SPEC, RW>
pub fn pwm_mode(self) -> RegisterFieldBool<3, 1, 0, Timer0CtrlReg_SPEC, RW>
0 = PWM signals are ‘1’ during high time. 1 = PWM signals send out the (fast) clock divided by 2 during high time. So it will be in the range of 1 to 8 MHz.
Sourcepub fn tim0_clk_div(self) -> RegisterFieldBool<2, 1, 0, Timer0CtrlReg_SPEC, RW>
pub fn tim0_clk_div(self) -> RegisterFieldBool<2, 1, 0, Timer0CtrlReg_SPEC, RW>
1 = Timer0 uses selected clock frequency as is. 0 = Timer0 uses selected clock frequency divided by 10. Note that this applies only to the ON-counter.
Sourcepub fn tim0_clk_sel(self) -> RegisterFieldBool<1, 1, 0, Timer0CtrlReg_SPEC, RW>
pub fn tim0_clk_sel(self) -> RegisterFieldBool<1, 1, 0, Timer0CtrlReg_SPEC, RW>
1 = Timer0 uses 16, 8, 4 or 2 MHz (fast) clock frequency. 0 = Timer0 uses LP clock
Sourcepub fn tim0_ctrl(self) -> RegisterFieldBool<0, 1, 0, Timer0CtrlReg_SPEC, RW>
pub fn tim0_ctrl(self) -> RegisterFieldBool<0, 1, 0, Timer0CtrlReg_SPEC, RW>
0 = Timer0 is off and in reset state. 1 = Timer0 is running.
Trait Implementations§
Source§impl Default for Timer0CtrlReg
impl Default for Timer0CtrlReg
Source§fn default() -> Timer0CtrlReg
fn default() -> Timer0CtrlReg
Returns the “default value” for a type. Read more