da14531_pac/
timer0.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:44:12 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"TIMER0 registers"]
28unsafe impl ::core::marker::Send for super::Timer0 {}
29unsafe impl ::core::marker::Sync for super::Timer0 {}
30impl super::Timer0 {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Defines end Cycle for PWM2"]
38    #[inline(always)]
39    pub const fn pwm2_end_cycle(
40        &self,
41    ) -> &'static crate::common::Reg<self::Pwm2EndCycle_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::Pwm2EndCycle_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(22usize),
45            )
46        }
47    }
48
49    #[doc = "Defines start Cycle for PWM2"]
50    #[inline(always)]
51    pub const fn pwm2_start_cycle(
52        &self,
53    ) -> &'static crate::common::Reg<self::Pwm2StartCycle_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::Pwm2StartCycle_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(10usize),
57            )
58        }
59    }
60
61    #[doc = "Defines end Cycle for PWM3"]
62    #[inline(always)]
63    pub const fn pwm3_end_cycle(
64        &self,
65    ) -> &'static crate::common::Reg<self::Pwm3EndCycle_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::Pwm3EndCycle_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(24usize),
69            )
70        }
71    }
72
73    #[doc = "Defines start Cycle for PWM3"]
74    #[inline(always)]
75    pub const fn pwm3_start_cycle(
76        &self,
77    ) -> &'static crate::common::Reg<self::Pwm3StartCycle_SPEC, crate::common::RW> {
78        unsafe {
79            crate::common::Reg::<self::Pwm3StartCycle_SPEC, crate::common::RW>::from_ptr(
80                self._svd2pac_as_ptr().add(12usize),
81            )
82        }
83    }
84
85    #[doc = "Defines end Cycle for PWM4"]
86    #[inline(always)]
87    pub const fn pwm4_end_cycle(
88        &self,
89    ) -> &'static crate::common::Reg<self::Pwm4EndCycle_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::Pwm4EndCycle_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(26usize),
93            )
94        }
95    }
96
97    #[doc = "Defines start Cycle for PWM4"]
98    #[inline(always)]
99    pub const fn pwm4_start_cycle(
100        &self,
101    ) -> &'static crate::common::Reg<self::Pwm4StartCycle_SPEC, crate::common::RW> {
102        unsafe {
103            crate::common::Reg::<self::Pwm4StartCycle_SPEC, crate::common::RW>::from_ptr(
104                self._svd2pac_as_ptr().add(14usize),
105            )
106        }
107    }
108
109    #[doc = "Defines end Cycle for PWM5"]
110    #[inline(always)]
111    pub const fn pwm5_end_cycle(
112        &self,
113    ) -> &'static crate::common::Reg<self::Pwm5EndCycle_SPEC, crate::common::RW> {
114        unsafe {
115            crate::common::Reg::<self::Pwm5EndCycle_SPEC, crate::common::RW>::from_ptr(
116                self._svd2pac_as_ptr().add(28usize),
117            )
118        }
119    }
120
121    #[doc = "Defines start Cycle for PWM5"]
122    #[inline(always)]
123    pub const fn pwm5_start_cycle(
124        &self,
125    ) -> &'static crate::common::Reg<self::Pwm5StartCycle_SPEC, crate::common::RW> {
126        unsafe {
127            crate::common::Reg::<self::Pwm5StartCycle_SPEC, crate::common::RW>::from_ptr(
128                self._svd2pac_as_ptr().add(16usize),
129            )
130        }
131    }
132
133    #[doc = "Defines end Cycle for PWM6"]
134    #[inline(always)]
135    pub const fn pwm6_end_cycle(
136        &self,
137    ) -> &'static crate::common::Reg<self::Pwm6EndCycle_SPEC, crate::common::RW> {
138        unsafe {
139            crate::common::Reg::<self::Pwm6EndCycle_SPEC, crate::common::RW>::from_ptr(
140                self._svd2pac_as_ptr().add(30usize),
141            )
142        }
143    }
144
145    #[doc = "Defines start Cycle for PWM6"]
146    #[inline(always)]
147    pub const fn pwm6_start_cycle(
148        &self,
149    ) -> &'static crate::common::Reg<self::Pwm6StartCycle_SPEC, crate::common::RW> {
150        unsafe {
151            crate::common::Reg::<self::Pwm6StartCycle_SPEC, crate::common::RW>::from_ptr(
152                self._svd2pac_as_ptr().add(18usize),
153            )
154        }
155    }
156
157    #[doc = "Defines end Cycle for PWM7"]
158    #[inline(always)]
159    pub const fn pwm7_end_cycle(
160        &self,
161    ) -> &'static crate::common::Reg<self::Pwm7EndCycle_SPEC, crate::common::RW> {
162        unsafe {
163            crate::common::Reg::<self::Pwm7EndCycle_SPEC, crate::common::RW>::from_ptr(
164                self._svd2pac_as_ptr().add(32usize),
165            )
166        }
167    }
168
169    #[doc = "Defines start Cycle for PWM7"]
170    #[inline(always)]
171    pub const fn pwm7_start_cycle(
172        &self,
173    ) -> &'static crate::common::Reg<self::Pwm7StartCycle_SPEC, crate::common::RW> {
174        unsafe {
175            crate::common::Reg::<self::Pwm7StartCycle_SPEC, crate::common::RW>::from_ptr(
176                self._svd2pac_as_ptr().add(20usize),
177            )
178        }
179    }
180
181    #[doc = "Timer0 control register"]
182    #[inline(always)]
183    pub const fn timer0_ctrl_reg(
184        &self,
185    ) -> &'static crate::common::Reg<self::Timer0CtrlReg_SPEC, crate::common::RW> {
186        unsafe {
187            crate::common::Reg::<self::Timer0CtrlReg_SPEC, crate::common::RW>::from_ptr(
188                self._svd2pac_as_ptr().add(0usize),
189            )
190        }
191    }
192
193    #[doc = "Timer0 on control register"]
194    #[inline(always)]
195    pub const fn timer0_on_reg(
196        &self,
197    ) -> &'static crate::common::Reg<self::Timer0OnReg_SPEC, crate::common::RW> {
198        unsafe {
199            crate::common::Reg::<self::Timer0OnReg_SPEC, crate::common::RW>::from_ptr(
200                self._svd2pac_as_ptr().add(2usize),
201            )
202        }
203    }
204
205    #[doc = "16 bits reload value for Timer0"]
206    #[inline(always)]
207    pub const fn timer0_reload_m_reg(
208        &self,
209    ) -> &'static crate::common::Reg<self::Timer0ReloadMReg_SPEC, crate::common::RW> {
210        unsafe {
211            crate::common::Reg::<self::Timer0ReloadMReg_SPEC, crate::common::RW>::from_ptr(
212                self._svd2pac_as_ptr().add(4usize),
213            )
214        }
215    }
216
217    #[doc = "16 bits reload value for Timer0"]
218    #[inline(always)]
219    pub const fn timer0_reload_n_reg(
220        &self,
221    ) -> &'static crate::common::Reg<self::Timer0ReloadNReg_SPEC, crate::common::RW> {
222        unsafe {
223            crate::common::Reg::<self::Timer0ReloadNReg_SPEC, crate::common::RW>::from_ptr(
224                self._svd2pac_as_ptr().add(6usize),
225            )
226        }
227    }
228
229    #[doc = "PWM 2,3,4,5,6,7 Control"]
230    #[inline(always)]
231    pub const fn triple_pwm_ctrl_reg(
232        &self,
233    ) -> &'static crate::common::Reg<self::TriplePwmCtrlReg_SPEC, crate::common::RW> {
234        unsafe {
235            crate::common::Reg::<self::TriplePwmCtrlReg_SPEC, crate::common::RW>::from_ptr(
236                self._svd2pac_as_ptr().add(34usize),
237            )
238        }
239    }
240
241    #[doc = "Frequency for PWM 2,3,4,5,6 and 7"]
242    #[inline(always)]
243    pub const fn triple_pwm_frequency(
244        &self,
245    ) -> &'static crate::common::Reg<self::TriplePwmFrequency_SPEC, crate::common::RW> {
246        unsafe {
247            crate::common::Reg::<self::TriplePwmFrequency_SPEC, crate::common::RW>::from_ptr(
248                self._svd2pac_as_ptr().add(8usize),
249            )
250        }
251    }
252}
253#[doc(hidden)]
254#[derive(Copy, Clone, Eq, PartialEq)]
255pub struct Pwm2EndCycle_SPEC;
256impl crate::sealed::RegSpec for Pwm2EndCycle_SPEC {
257    type DataType = u16;
258}
259
260#[doc = "Defines end Cycle for PWM2"]
261pub type Pwm2EndCycle = crate::RegValueT<Pwm2EndCycle_SPEC>;
262
263impl Pwm2EndCycle {
264    #[doc = "Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1"]
265    #[inline(always)]
266    pub fn end_cycle(
267        self,
268    ) -> crate::common::RegisterField<0, 0x3fff, 1, 0, u16, u16, Pwm2EndCycle_SPEC, crate::common::RW>
269    {
270        crate::common::RegisterField::<
271            0,
272            0x3fff,
273            1,
274            0,
275            u16,
276            u16,
277            Pwm2EndCycle_SPEC,
278            crate::common::RW,
279        >::from_register(self, 0)
280    }
281}
282impl ::core::default::Default for Pwm2EndCycle {
283    #[inline(always)]
284    fn default() -> Pwm2EndCycle {
285        <crate::RegValueT<Pwm2EndCycle_SPEC> as RegisterValue<_>>::new(0)
286    }
287}
288
289#[doc(hidden)]
290#[derive(Copy, Clone, Eq, PartialEq)]
291pub struct Pwm2StartCycle_SPEC;
292impl crate::sealed::RegSpec for Pwm2StartCycle_SPEC {
293    type DataType = u16;
294}
295
296#[doc = "Defines start Cycle for PWM2"]
297pub type Pwm2StartCycle = crate::RegValueT<Pwm2StartCycle_SPEC>;
298
299impl Pwm2StartCycle {
300    #[doc = "Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0"]
301    #[inline(always)]
302    pub fn start_cycle(
303        self,
304    ) -> crate::common::RegisterField<
305        0,
306        0x3fff,
307        1,
308        0,
309        u16,
310        u16,
311        Pwm2StartCycle_SPEC,
312        crate::common::RW,
313    > {
314        crate::common::RegisterField::<
315            0,
316            0x3fff,
317            1,
318            0,
319            u16,
320            u16,
321            Pwm2StartCycle_SPEC,
322            crate::common::RW,
323        >::from_register(self, 0)
324    }
325}
326impl ::core::default::Default for Pwm2StartCycle {
327    #[inline(always)]
328    fn default() -> Pwm2StartCycle {
329        <crate::RegValueT<Pwm2StartCycle_SPEC> as RegisterValue<_>>::new(0)
330    }
331}
332
333#[doc(hidden)]
334#[derive(Copy, Clone, Eq, PartialEq)]
335pub struct Pwm3EndCycle_SPEC;
336impl crate::sealed::RegSpec for Pwm3EndCycle_SPEC {
337    type DataType = u16;
338}
339
340#[doc = "Defines end Cycle for PWM3"]
341pub type Pwm3EndCycle = crate::RegValueT<Pwm3EndCycle_SPEC>;
342
343impl Pwm3EndCycle {
344    #[doc = "Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1"]
345    #[inline(always)]
346    pub fn end_cycle(
347        self,
348    ) -> crate::common::RegisterField<0, 0x3fff, 1, 0, u16, u16, Pwm3EndCycle_SPEC, crate::common::RW>
349    {
350        crate::common::RegisterField::<
351            0,
352            0x3fff,
353            1,
354            0,
355            u16,
356            u16,
357            Pwm3EndCycle_SPEC,
358            crate::common::RW,
359        >::from_register(self, 0)
360    }
361}
362impl ::core::default::Default for Pwm3EndCycle {
363    #[inline(always)]
364    fn default() -> Pwm3EndCycle {
365        <crate::RegValueT<Pwm3EndCycle_SPEC> as RegisterValue<_>>::new(0)
366    }
367}
368
369#[doc(hidden)]
370#[derive(Copy, Clone, Eq, PartialEq)]
371pub struct Pwm3StartCycle_SPEC;
372impl crate::sealed::RegSpec for Pwm3StartCycle_SPEC {
373    type DataType = u16;
374}
375
376#[doc = "Defines start Cycle for PWM3"]
377pub type Pwm3StartCycle = crate::RegValueT<Pwm3StartCycle_SPEC>;
378
379impl Pwm3StartCycle {
380    #[doc = "Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0"]
381    #[inline(always)]
382    pub fn start_cycle(
383        self,
384    ) -> crate::common::RegisterField<
385        0,
386        0x3fff,
387        1,
388        0,
389        u16,
390        u16,
391        Pwm3StartCycle_SPEC,
392        crate::common::RW,
393    > {
394        crate::common::RegisterField::<
395            0,
396            0x3fff,
397            1,
398            0,
399            u16,
400            u16,
401            Pwm3StartCycle_SPEC,
402            crate::common::RW,
403        >::from_register(self, 0)
404    }
405}
406impl ::core::default::Default for Pwm3StartCycle {
407    #[inline(always)]
408    fn default() -> Pwm3StartCycle {
409        <crate::RegValueT<Pwm3StartCycle_SPEC> as RegisterValue<_>>::new(0)
410    }
411}
412
413#[doc(hidden)]
414#[derive(Copy, Clone, Eq, PartialEq)]
415pub struct Pwm4EndCycle_SPEC;
416impl crate::sealed::RegSpec for Pwm4EndCycle_SPEC {
417    type DataType = u16;
418}
419
420#[doc = "Defines end Cycle for PWM4"]
421pub type Pwm4EndCycle = crate::RegValueT<Pwm4EndCycle_SPEC>;
422
423impl Pwm4EndCycle {
424    #[doc = "Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1"]
425    #[inline(always)]
426    pub fn end_cycle(
427        self,
428    ) -> crate::common::RegisterField<0, 0x3fff, 1, 0, u16, u16, Pwm4EndCycle_SPEC, crate::common::RW>
429    {
430        crate::common::RegisterField::<
431            0,
432            0x3fff,
433            1,
434            0,
435            u16,
436            u16,
437            Pwm4EndCycle_SPEC,
438            crate::common::RW,
439        >::from_register(self, 0)
440    }
441}
442impl ::core::default::Default for Pwm4EndCycle {
443    #[inline(always)]
444    fn default() -> Pwm4EndCycle {
445        <crate::RegValueT<Pwm4EndCycle_SPEC> as RegisterValue<_>>::new(0)
446    }
447}
448
449#[doc(hidden)]
450#[derive(Copy, Clone, Eq, PartialEq)]
451pub struct Pwm4StartCycle_SPEC;
452impl crate::sealed::RegSpec for Pwm4StartCycle_SPEC {
453    type DataType = u16;
454}
455
456#[doc = "Defines start Cycle for PWM4"]
457pub type Pwm4StartCycle = crate::RegValueT<Pwm4StartCycle_SPEC>;
458
459impl Pwm4StartCycle {
460    #[doc = "Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0"]
461    #[inline(always)]
462    pub fn start_cycle(
463        self,
464    ) -> crate::common::RegisterField<
465        0,
466        0x3fff,
467        1,
468        0,
469        u16,
470        u16,
471        Pwm4StartCycle_SPEC,
472        crate::common::RW,
473    > {
474        crate::common::RegisterField::<
475            0,
476            0x3fff,
477            1,
478            0,
479            u16,
480            u16,
481            Pwm4StartCycle_SPEC,
482            crate::common::RW,
483        >::from_register(self, 0)
484    }
485}
486impl ::core::default::Default for Pwm4StartCycle {
487    #[inline(always)]
488    fn default() -> Pwm4StartCycle {
489        <crate::RegValueT<Pwm4StartCycle_SPEC> as RegisterValue<_>>::new(0)
490    }
491}
492
493#[doc(hidden)]
494#[derive(Copy, Clone, Eq, PartialEq)]
495pub struct Pwm5EndCycle_SPEC;
496impl crate::sealed::RegSpec for Pwm5EndCycle_SPEC {
497    type DataType = u16;
498}
499
500#[doc = "Defines end Cycle for PWM5"]
501pub type Pwm5EndCycle = crate::RegValueT<Pwm5EndCycle_SPEC>;
502
503impl Pwm5EndCycle {
504    #[doc = "Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1"]
505    #[inline(always)]
506    pub fn end_cycle(
507        self,
508    ) -> crate::common::RegisterField<0, 0x3fff, 1, 0, u16, u16, Pwm5EndCycle_SPEC, crate::common::RW>
509    {
510        crate::common::RegisterField::<
511            0,
512            0x3fff,
513            1,
514            0,
515            u16,
516            u16,
517            Pwm5EndCycle_SPEC,
518            crate::common::RW,
519        >::from_register(self, 0)
520    }
521}
522impl ::core::default::Default for Pwm5EndCycle {
523    #[inline(always)]
524    fn default() -> Pwm5EndCycle {
525        <crate::RegValueT<Pwm5EndCycle_SPEC> as RegisterValue<_>>::new(0)
526    }
527}
528
529#[doc(hidden)]
530#[derive(Copy, Clone, Eq, PartialEq)]
531pub struct Pwm5StartCycle_SPEC;
532impl crate::sealed::RegSpec for Pwm5StartCycle_SPEC {
533    type DataType = u16;
534}
535
536#[doc = "Defines start Cycle for PWM5"]
537pub type Pwm5StartCycle = crate::RegValueT<Pwm5StartCycle_SPEC>;
538
539impl Pwm5StartCycle {
540    #[doc = "Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0"]
541    #[inline(always)]
542    pub fn start_cycle(
543        self,
544    ) -> crate::common::RegisterField<
545        0,
546        0x3fff,
547        1,
548        0,
549        u16,
550        u16,
551        Pwm5StartCycle_SPEC,
552        crate::common::RW,
553    > {
554        crate::common::RegisterField::<
555            0,
556            0x3fff,
557            1,
558            0,
559            u16,
560            u16,
561            Pwm5StartCycle_SPEC,
562            crate::common::RW,
563        >::from_register(self, 0)
564    }
565}
566impl ::core::default::Default for Pwm5StartCycle {
567    #[inline(always)]
568    fn default() -> Pwm5StartCycle {
569        <crate::RegValueT<Pwm5StartCycle_SPEC> as RegisterValue<_>>::new(0)
570    }
571}
572
573#[doc(hidden)]
574#[derive(Copy, Clone, Eq, PartialEq)]
575pub struct Pwm6EndCycle_SPEC;
576impl crate::sealed::RegSpec for Pwm6EndCycle_SPEC {
577    type DataType = u16;
578}
579
580#[doc = "Defines end Cycle for PWM6"]
581pub type Pwm6EndCycle = crate::RegValueT<Pwm6EndCycle_SPEC>;
582
583impl Pwm6EndCycle {
584    #[doc = "Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1"]
585    #[inline(always)]
586    pub fn end_cycle(
587        self,
588    ) -> crate::common::RegisterField<0, 0x3fff, 1, 0, u16, u16, Pwm6EndCycle_SPEC, crate::common::RW>
589    {
590        crate::common::RegisterField::<
591            0,
592            0x3fff,
593            1,
594            0,
595            u16,
596            u16,
597            Pwm6EndCycle_SPEC,
598            crate::common::RW,
599        >::from_register(self, 0)
600    }
601}
602impl ::core::default::Default for Pwm6EndCycle {
603    #[inline(always)]
604    fn default() -> Pwm6EndCycle {
605        <crate::RegValueT<Pwm6EndCycle_SPEC> as RegisterValue<_>>::new(0)
606    }
607}
608
609#[doc(hidden)]
610#[derive(Copy, Clone, Eq, PartialEq)]
611pub struct Pwm6StartCycle_SPEC;
612impl crate::sealed::RegSpec for Pwm6StartCycle_SPEC {
613    type DataType = u16;
614}
615
616#[doc = "Defines start Cycle for PWM6"]
617pub type Pwm6StartCycle = crate::RegValueT<Pwm6StartCycle_SPEC>;
618
619impl Pwm6StartCycle {
620    #[doc = "Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0"]
621    #[inline(always)]
622    pub fn start_cycle(
623        self,
624    ) -> crate::common::RegisterField<
625        0,
626        0x3fff,
627        1,
628        0,
629        u16,
630        u16,
631        Pwm6StartCycle_SPEC,
632        crate::common::RW,
633    > {
634        crate::common::RegisterField::<
635            0,
636            0x3fff,
637            1,
638            0,
639            u16,
640            u16,
641            Pwm6StartCycle_SPEC,
642            crate::common::RW,
643        >::from_register(self, 0)
644    }
645}
646impl ::core::default::Default for Pwm6StartCycle {
647    #[inline(always)]
648    fn default() -> Pwm6StartCycle {
649        <crate::RegValueT<Pwm6StartCycle_SPEC> as RegisterValue<_>>::new(0)
650    }
651}
652
653#[doc(hidden)]
654#[derive(Copy, Clone, Eq, PartialEq)]
655pub struct Pwm7EndCycle_SPEC;
656impl crate::sealed::RegSpec for Pwm7EndCycle_SPEC {
657    type DataType = u16;
658}
659
660#[doc = "Defines end Cycle for PWM7"]
661pub type Pwm7EndCycle = crate::RegValueT<Pwm7EndCycle_SPEC>;
662
663impl Pwm7EndCycle {
664    #[doc = "Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1"]
665    #[inline(always)]
666    pub fn end_cycle(
667        self,
668    ) -> crate::common::RegisterField<0, 0x3fff, 1, 0, u16, u16, Pwm7EndCycle_SPEC, crate::common::RW>
669    {
670        crate::common::RegisterField::<
671            0,
672            0x3fff,
673            1,
674            0,
675            u16,
676            u16,
677            Pwm7EndCycle_SPEC,
678            crate::common::RW,
679        >::from_register(self, 0)
680    }
681}
682impl ::core::default::Default for Pwm7EndCycle {
683    #[inline(always)]
684    fn default() -> Pwm7EndCycle {
685        <crate::RegValueT<Pwm7EndCycle_SPEC> as RegisterValue<_>>::new(0)
686    }
687}
688
689#[doc(hidden)]
690#[derive(Copy, Clone, Eq, PartialEq)]
691pub struct Pwm7StartCycle_SPEC;
692impl crate::sealed::RegSpec for Pwm7StartCycle_SPEC {
693    type DataType = u16;
694}
695
696#[doc = "Defines start Cycle for PWM7"]
697pub type Pwm7StartCycle = crate::RegValueT<Pwm7StartCycle_SPEC>;
698
699impl Pwm7StartCycle {
700    #[doc = "Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0"]
701    #[inline(always)]
702    pub fn start_cycle(
703        self,
704    ) -> crate::common::RegisterField<
705        0,
706        0x3fff,
707        1,
708        0,
709        u16,
710        u16,
711        Pwm7StartCycle_SPEC,
712        crate::common::RW,
713    > {
714        crate::common::RegisterField::<
715            0,
716            0x3fff,
717            1,
718            0,
719            u16,
720            u16,
721            Pwm7StartCycle_SPEC,
722            crate::common::RW,
723        >::from_register(self, 0)
724    }
725}
726impl ::core::default::Default for Pwm7StartCycle {
727    #[inline(always)]
728    fn default() -> Pwm7StartCycle {
729        <crate::RegValueT<Pwm7StartCycle_SPEC> as RegisterValue<_>>::new(0)
730    }
731}
732
733#[doc(hidden)]
734#[derive(Copy, Clone, Eq, PartialEq)]
735pub struct Timer0CtrlReg_SPEC;
736impl crate::sealed::RegSpec for Timer0CtrlReg_SPEC {
737    type DataType = u16;
738}
739
740#[doc = "Timer0 control register"]
741pub type Timer0CtrlReg = crate::RegValueT<Timer0CtrlReg_SPEC>;
742
743impl Timer0CtrlReg {
744    #[doc = "0 = PWM signals are \'1\' during high time.\n1 = PWM signals send out the (fast) clock divided by 2 during high time. So it will be in the range of 1 to 8 MHz."]
745    #[inline(always)]
746    pub fn pwm_mode(
747        self,
748    ) -> crate::common::RegisterFieldBool<3, 1, 0, Timer0CtrlReg_SPEC, crate::common::RW> {
749        crate::common::RegisterFieldBool::<3,1,0,Timer0CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
750    }
751
752    #[doc = "1 = Timer0 uses selected clock frequency as is.\n0 = Timer0 uses selected clock frequency divided by 10.\nNote that this applies only to the ON-counter."]
753    #[inline(always)]
754    pub fn tim0_clk_div(
755        self,
756    ) -> crate::common::RegisterFieldBool<2, 1, 0, Timer0CtrlReg_SPEC, crate::common::RW> {
757        crate::common::RegisterFieldBool::<2,1,0,Timer0CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
758    }
759
760    #[doc = "1 = Timer0 uses 16, 8, 4 or 2 MHz (fast) clock frequency.\n0 = Timer0 uses LP clock"]
761    #[inline(always)]
762    pub fn tim0_clk_sel(
763        self,
764    ) -> crate::common::RegisterFieldBool<1, 1, 0, Timer0CtrlReg_SPEC, crate::common::RW> {
765        crate::common::RegisterFieldBool::<1,1,0,Timer0CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
766    }
767
768    #[doc = "0 = Timer0 is off and in reset state.\n1 = Timer0 is running."]
769    #[inline(always)]
770    pub fn tim0_ctrl(
771        self,
772    ) -> crate::common::RegisterFieldBool<0, 1, 0, Timer0CtrlReg_SPEC, crate::common::RW> {
773        crate::common::RegisterFieldBool::<0,1,0,Timer0CtrlReg_SPEC,crate::common::RW>::from_register(self,0)
774    }
775}
776impl ::core::default::Default for Timer0CtrlReg {
777    #[inline(always)]
778    fn default() -> Timer0CtrlReg {
779        <crate::RegValueT<Timer0CtrlReg_SPEC> as RegisterValue<_>>::new(0)
780    }
781}
782
783#[doc(hidden)]
784#[derive(Copy, Clone, Eq, PartialEq)]
785pub struct Timer0OnReg_SPEC;
786impl crate::sealed::RegSpec for Timer0OnReg_SPEC {
787    type DataType = u16;
788}
789
790#[doc = "Timer0 on control register"]
791pub type Timer0OnReg = crate::RegValueT<Timer0OnReg_SPEC>;
792
793impl Timer0OnReg {
794    #[doc = "Timer0 On reload value:\nIf read the actual ON-counter value is returned"]
795    #[inline(always)]
796    pub fn tim0_on(
797        self,
798    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Timer0OnReg_SPEC, crate::common::RW>
799    {
800        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Timer0OnReg_SPEC,crate::common::RW>::from_register(self,0)
801    }
802}
803impl ::core::default::Default for Timer0OnReg {
804    #[inline(always)]
805    fn default() -> Timer0OnReg {
806        <crate::RegValueT<Timer0OnReg_SPEC> as RegisterValue<_>>::new(0)
807    }
808}
809
810#[doc(hidden)]
811#[derive(Copy, Clone, Eq, PartialEq)]
812pub struct Timer0ReloadMReg_SPEC;
813impl crate::sealed::RegSpec for Timer0ReloadMReg_SPEC {
814    type DataType = u16;
815}
816
817#[doc = "16 bits reload value for Timer0"]
818pub type Timer0ReloadMReg = crate::RegValueT<Timer0ReloadMReg_SPEC>;
819
820impl Timer0ReloadMReg {
821    #[doc = "Timer0 \'high\' reload value\nIf read the actual T0-counter value is returned"]
822    #[inline(always)]
823    pub fn tim0_m(
824        self,
825    ) -> crate::common::RegisterField<
826        0,
827        0xffff,
828        1,
829        0,
830        u16,
831        u16,
832        Timer0ReloadMReg_SPEC,
833        crate::common::RW,
834    > {
835        crate::common::RegisterField::<
836            0,
837            0xffff,
838            1,
839            0,
840            u16,
841            u16,
842            Timer0ReloadMReg_SPEC,
843            crate::common::RW,
844        >::from_register(self, 0)
845    }
846}
847impl ::core::default::Default for Timer0ReloadMReg {
848    #[inline(always)]
849    fn default() -> Timer0ReloadMReg {
850        <crate::RegValueT<Timer0ReloadMReg_SPEC> as RegisterValue<_>>::new(0)
851    }
852}
853
854#[doc(hidden)]
855#[derive(Copy, Clone, Eq, PartialEq)]
856pub struct Timer0ReloadNReg_SPEC;
857impl crate::sealed::RegSpec for Timer0ReloadNReg_SPEC {
858    type DataType = u16;
859}
860
861#[doc = "16 bits reload value for Timer0"]
862pub type Timer0ReloadNReg = crate::RegValueT<Timer0ReloadNReg_SPEC>;
863
864impl Timer0ReloadNReg {
865    #[doc = "Timer0 \'low\' reload value:\nIf read the actual T0-counter value is returned"]
866    #[inline(always)]
867    pub fn tim0_n(
868        self,
869    ) -> crate::common::RegisterField<
870        0,
871        0xffff,
872        1,
873        0,
874        u16,
875        u16,
876        Timer0ReloadNReg_SPEC,
877        crate::common::RW,
878    > {
879        crate::common::RegisterField::<
880            0,
881            0xffff,
882            1,
883            0,
884            u16,
885            u16,
886            Timer0ReloadNReg_SPEC,
887            crate::common::RW,
888        >::from_register(self, 0)
889    }
890}
891impl ::core::default::Default for Timer0ReloadNReg {
892    #[inline(always)]
893    fn default() -> Timer0ReloadNReg {
894        <crate::RegValueT<Timer0ReloadNReg_SPEC> as RegisterValue<_>>::new(0)
895    }
896}
897
898#[doc(hidden)]
899#[derive(Copy, Clone, Eq, PartialEq)]
900pub struct TriplePwmCtrlReg_SPEC;
901impl crate::sealed::RegSpec for TriplePwmCtrlReg_SPEC {
902    type DataType = u16;
903}
904
905#[doc = "PWM 2,3,4,5,6,7 Control"]
906pub type TriplePwmCtrlReg = crate::RegValueT<TriplePwmCtrlReg_SPEC>;
907
908impl TriplePwmCtrlReg {
909    #[doc = "1 = Timer2 uses 16, 8, 4 or 2 MHz (fast) clock frequency.\n0 = Timer2 uses LP clock"]
910    #[inline(always)]
911    pub fn triple_pwm_clk_sel(
912        self,
913    ) -> crate::common::RegisterFieldBool<3, 1, 0, TriplePwmCtrlReg_SPEC, crate::common::RW> {
914        crate::common::RegisterFieldBool::<3,1,0,TriplePwmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
915    }
916
917    #[doc = "\'1\' = HW can pause PWM 2,3,4,5,6,7"]
918    #[inline(always)]
919    pub fn hw_pause_en(
920        self,
921    ) -> crate::common::RegisterFieldBool<2, 1, 0, TriplePwmCtrlReg_SPEC, crate::common::RW> {
922        crate::common::RegisterFieldBool::<2,1,0,TriplePwmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
923    }
924
925    #[doc = "\'1\' = PWM 2 3 4 5 6 7 are paused"]
926    #[inline(always)]
927    pub fn sw_pause_en(
928        self,
929    ) -> crate::common::RegisterFieldBool<1, 1, 0, TriplePwmCtrlReg_SPEC, crate::common::RW> {
930        crate::common::RegisterFieldBool::<1,1,0,TriplePwmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
931    }
932
933    #[doc = "\'1\' = enable PWM 2 3 4 5 6 7"]
934    #[inline(always)]
935    pub fn triple_pwm_enable(
936        self,
937    ) -> crate::common::RegisterFieldBool<0, 1, 0, TriplePwmCtrlReg_SPEC, crate::common::RW> {
938        crate::common::RegisterFieldBool::<0,1,0,TriplePwmCtrlReg_SPEC,crate::common::RW>::from_register(self,0)
939    }
940}
941impl ::core::default::Default for TriplePwmCtrlReg {
942    #[inline(always)]
943    fn default() -> TriplePwmCtrlReg {
944        <crate::RegValueT<TriplePwmCtrlReg_SPEC> as RegisterValue<_>>::new(4)
945    }
946}
947
948#[doc(hidden)]
949#[derive(Copy, Clone, Eq, PartialEq)]
950pub struct TriplePwmFrequency_SPEC;
951impl crate::sealed::RegSpec for TriplePwmFrequency_SPEC {
952    type DataType = u16;
953}
954
955#[doc = "Frequency for PWM 2,3,4,5,6 and 7"]
956pub type TriplePwmFrequency = crate::RegValueT<TriplePwmFrequency_SPEC>;
957
958impl TriplePwmFrequency {
959    #[doc = "Defines the frequeancy of PWM 2,3,4,5,,6 and 7. pwm freq = module Frequency / (value+1)\nmodule frequency is the LP_CLK when TRIPLE_PWM_CLK_SEL=0 else is the sys_clk divided by TMR_DIV"]
960    #[inline(always)]
961    pub fn pwm_freq(
962        self,
963    ) -> crate::common::RegisterField<
964        0,
965        0x3fff,
966        1,
967        0,
968        u16,
969        u16,
970        TriplePwmFrequency_SPEC,
971        crate::common::RW,
972    > {
973        crate::common::RegisterField::<
974            0,
975            0x3fff,
976            1,
977            0,
978            u16,
979            u16,
980            TriplePwmFrequency_SPEC,
981            crate::common::RW,
982        >::from_register(self, 0)
983    }
984}
985impl ::core::default::Default for TriplePwmFrequency {
986    #[inline(always)]
987    fn default() -> TriplePwmFrequency {
988        <crate::RegValueT<TriplePwmFrequency_SPEC> as RegisterValue<_>>::new(0)
989    }
990}
da14531_pac/timer0.rs

da14531_pac/
timer0.rs
