Struct IOMMU

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pub struct IOMMU { /* private fields */ }

Expand description

I/O Memory Management Unit

Implementations§

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impl IOMMU

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pub const PTR: *const RegisterBlock

Pointer to the register block

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pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

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pub unsafe fn steal() -> Self

Steal an instance of this peripheral

§Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>§

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pub fn iommu_reset(&self) -> &IOMMU_RESET

0x10 - IOMMU Reset Register

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pub fn iommu_enable(&self) -> &IOMMU_ENABLE

0x20 - IOMMU Enable Register

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pub fn iommu_bypass(&self) -> &IOMMU_BYPASS

0x30 - IOMMU Bypass Register

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pub fn iommu_auto_gating(&self) -> &IOMMU_AUTO_GATING

0x40 - IOMMU Auto Gating Register

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pub fn iommu_wbuf_ctrl(&self) -> &IOMMU_WBUF_CTRL

0x44 - IOMMU Write Buffer Control Register

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pub fn iommu_ooo_ctrl(&self) -> &IOMMU_OOO_CTRL

0x48 - IOMMU Out of Order Control Register

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pub fn iommu_4kb_bdy_prt_ctrl(&self) -> &IOMMU_4KB_BDY_PRT_CTRL

0x4c - IOMMU 4KB Boundary Protect Control Register

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pub fn iommu_ttb(&self) -> &IOMMU_TTB

0x50 - IOMMU Translation Table Base Register

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pub fn iommu_tlb_enable(&self) -> &IOMMU_TLB_ENABLE

0x60 - IOMMU TLB Enable Register

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pub fn iommu_tlb_prefetch(&self) -> &IOMMU_TLB_PREFETCH

0x70 - IOMMU TLB Prefetch Register

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pub fn iommu_tlb_flush_enable(&self) -> &IOMMU_TLB_FLUSH_ENABLE

0x80 - IOMMU TLB Flush Enable Register

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pub fn iommu_tlb_ivld_mode_sel(&self) -> &IOMMU_TLB_IVLD_MODE_SEL

0x84 - IOMMU TLB Invalidation Mode Select Register

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pub fn iommu_tlb_ivld_sta_addr(&self) -> &IOMMU_TLB_IVLD_STA_ADDR

0x88 - IOMMU TLB Invalidation Start Address Register

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pub fn iommu_tlb_ivld_end_addr(&self) -> &IOMMU_TLB_IVLD_END_ADDR

0x8c - IOMMU TLB Invalidation End Address Register

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pub fn iommu_tlb_ivld_addr(&self) -> &IOMMU_TLB_IVLD_ADDR

0x90 - IOMMU TLB Invalidation Address Register

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pub fn iommu_tlb_ivld_addr_mask(&self) -> &IOMMU_TLB_IVLD_ADDR_MASK

0x94 - IOMMU TLB Invalidation Address Mask Register

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pub fn iommu_tlb_ivld_enable(&self) -> &IOMMU_TLB_IVLD_ENABLE

0x98 - IOMMU TLB Invalidation Enable Register

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pub fn iommu_pc_ivld_mode_sel(&self) -> &IOMMU_PC_IVLD_MODE_SEL

0x9c - IOMMU PC Invalidation Mode Select Register

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pub fn iommu_pc_ivld_addr(&self) -> &IOMMU_PC_IVLD_ADDR

0xa0 - IOMMU PC Invalidation Address Register

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pub fn iommu_pc_ivld_sta_addr(&self) -> &IOMMU_PC_IVLD_STA_ADDR

0xa4 - IOMMU PC Invalidation Start Address Register

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pub fn iommu_pc_ivld_enable(&self) -> &IOMMU_PC_IVLD_ENABLE

0xa8 - IOMMU PC Invalidation Enable Register

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pub fn iommu_pc_ivld_end_addr(&self) -> &IOMMU_PC_IVLD_END_ADDR

0xac - IOMMU PC Invalidation End Address Register

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pub fn iommu_dm_aut_ctrl(&self, n: usize) -> &IOMMU_DM_AUT_CTRL

0xb0..0xd0 - IOMMU Domain Authority Control [i] Register

Software can set 15 different permission control types in IOMMU_DM_AUT_CTRL0-7. A default access control type is DOMAIN0. The read/write operation of DOMAIN1-15 is unlimited by default.

Software needs to set the index of the permission control domain corresponding to the page table item in the bit[7:4] of the Level2 page table, the default value is 0 (use domain 0), that is, the read/write operation is not controlled.

Setting REG_ARD_OVWT can mask the Domain control defined by IOMMU_DM_AUT_CTRL0-7. All Level2 page table type are covered by the type of REG_ARD_OVWT. The read/write operation is permitted by default.

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