d1_pac/
iommu.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    _reserved0: [u8; 0x10],
5    iommu_reset: IOMMU_RESET,
6    _reserved1: [u8; 0x0c],
7    iommu_enable: IOMMU_ENABLE,
8    _reserved2: [u8; 0x0c],
9    iommu_bypass: IOMMU_BYPASS,
10    _reserved3: [u8; 0x0c],
11    iommu_auto_gating: IOMMU_AUTO_GATING,
12    iommu_wbuf_ctrl: IOMMU_WBUF_CTRL,
13    iommu_ooo_ctrl: IOMMU_OOO_CTRL,
14    iommu_4kb_bdy_prt_ctrl: IOMMU_4KB_BDY_PRT_CTRL,
15    iommu_ttb: IOMMU_TTB,
16    _reserved8: [u8; 0x0c],
17    iommu_tlb_enable: IOMMU_TLB_ENABLE,
18    _reserved9: [u8; 0x0c],
19    iommu_tlb_prefetch: IOMMU_TLB_PREFETCH,
20    _reserved10: [u8; 0x0c],
21    iommu_tlb_flush_enable: IOMMU_TLB_FLUSH_ENABLE,
22    iommu_tlb_ivld_mode_sel: IOMMU_TLB_IVLD_MODE_SEL,
23    iommu_tlb_ivld_sta_addr: IOMMU_TLB_IVLD_STA_ADDR,
24    iommu_tlb_ivld_end_addr: IOMMU_TLB_IVLD_END_ADDR,
25    iommu_tlb_ivld_addr: IOMMU_TLB_IVLD_ADDR,
26    iommu_tlb_ivld_addr_mask: IOMMU_TLB_IVLD_ADDR_MASK,
27    iommu_tlb_ivld_enable: IOMMU_TLB_IVLD_ENABLE,
28    iommu_pc_ivld_mode_sel: IOMMU_PC_IVLD_MODE_SEL,
29    iommu_pc_ivld_addr: IOMMU_PC_IVLD_ADDR,
30    iommu_pc_ivld_sta_addr: IOMMU_PC_IVLD_STA_ADDR,
31    iommu_pc_ivld_enable: IOMMU_PC_IVLD_ENABLE,
32    iommu_pc_ivld_end_addr: IOMMU_PC_IVLD_END_ADDR,
33    iommu_dm_aut_ctrl: [IOMMU_DM_AUT_CTRL; 8],
34    iommu_dm_aut_ovwt: IOMMU_DM_AUT_OVWT,
35    _reserved24: [u8; 0x2c],
36    iommu_int_enable: IOMMU_INT_ENABLE,
37    iommu_int_clr: IOMMU_INT_CLR,
38    iommu_int_sta: IOMMU_INT_STA,
39    _reserved27: [u8; 0x04],
40    iommu_int_err_addr_tlb: [IOMMU_INT_ERR_ADDR_TLB; 7],
41    _reserved28: [u8; 0x04],
42    iommu_int_err_addr_l: [IOMMU_INT_ERR_ADDR_L; 2],
43    _reserved29: [u8; 0x18],
44    iommu_int_err_data_tlb: [IOMMU_INT_ERR_DATA_TLB; 7],
45    _reserved30: [u8; 0x04],
46    iommu_int_err_data_l: [IOMMU_INT_ERR_DATA_L; 2],
47    _reserved31: [u8; 0x08],
48    iommu_lpg_int: [IOMMU_LPG_INT; 2],
49    _reserved32: [u8; 0x08],
50    iommu_va: IOMMU_VA,
51    iommu_va_data: IOMMU_VA_DATA,
52    iommu_va_config: IOMMU_VA_CONFIG,
53    _reserved35: [u8; 0x64],
54    iommu_pmu_enable: IOMMU_PMU_ENABLE,
55    _reserved36: [u8; 0x0c],
56    iommu_pmu_clr: IOMMU_PMU_CLR,
57    _reserved37: [u8; 0x1c],
58    iommu_pmu_access_low: (),
59    _reserved38: [u8; 0x04],
60    iommu_pmu_access_high: (),
61    _reserved39: [u8; 0x04],
62    iommu_pmu_hit_low: (),
63    _reserved40: [u8; 0x04],
64    iommu_pmu_hit_high: (),
65    _reserved41: [u8; 0xc4],
66    iommu_pmu_tl_low: (),
67    _reserved42: [u8; 0x04],
68    iommu_pmu_tl_high: (),
69    _reserved43: [u8; 0x04],
70    iommu_pmu_ml: (),
71}
72impl RegisterBlock {
73    #[doc = "0x10 - IOMMU Reset Register"]
74    #[inline(always)]
75    pub const fn iommu_reset(&self) -> &IOMMU_RESET {
76        &self.iommu_reset
77    }
78    #[doc = "0x20 - IOMMU Enable Register"]
79    #[inline(always)]
80    pub const fn iommu_enable(&self) -> &IOMMU_ENABLE {
81        &self.iommu_enable
82    }
83    #[doc = "0x30 - IOMMU Bypass Register"]
84    #[inline(always)]
85    pub const fn iommu_bypass(&self) -> &IOMMU_BYPASS {
86        &self.iommu_bypass
87    }
88    #[doc = "0x40 - IOMMU Auto Gating Register"]
89    #[inline(always)]
90    pub const fn iommu_auto_gating(&self) -> &IOMMU_AUTO_GATING {
91        &self.iommu_auto_gating
92    }
93    #[doc = "0x44 - IOMMU Write Buffer Control Register"]
94    #[inline(always)]
95    pub const fn iommu_wbuf_ctrl(&self) -> &IOMMU_WBUF_CTRL {
96        &self.iommu_wbuf_ctrl
97    }
98    #[doc = "0x48 - IOMMU Out of Order Control Register"]
99    #[inline(always)]
100    pub const fn iommu_ooo_ctrl(&self) -> &IOMMU_OOO_CTRL {
101        &self.iommu_ooo_ctrl
102    }
103    #[doc = "0x4c - IOMMU 4KB Boundary Protect Control Register"]
104    #[inline(always)]
105    pub const fn iommu_4kb_bdy_prt_ctrl(&self) -> &IOMMU_4KB_BDY_PRT_CTRL {
106        &self.iommu_4kb_bdy_prt_ctrl
107    }
108    #[doc = "0x50 - IOMMU Translation Table Base Register"]
109    #[inline(always)]
110    pub const fn iommu_ttb(&self) -> &IOMMU_TTB {
111        &self.iommu_ttb
112    }
113    #[doc = "0x60 - IOMMU TLB Enable Register"]
114    #[inline(always)]
115    pub const fn iommu_tlb_enable(&self) -> &IOMMU_TLB_ENABLE {
116        &self.iommu_tlb_enable
117    }
118    #[doc = "0x70 - IOMMU TLB Prefetch Register"]
119    #[inline(always)]
120    pub const fn iommu_tlb_prefetch(&self) -> &IOMMU_TLB_PREFETCH {
121        &self.iommu_tlb_prefetch
122    }
123    #[doc = "0x80 - IOMMU TLB Flush Enable Register"]
124    #[inline(always)]
125    pub const fn iommu_tlb_flush_enable(&self) -> &IOMMU_TLB_FLUSH_ENABLE {
126        &self.iommu_tlb_flush_enable
127    }
128    #[doc = "0x84 - IOMMU TLB Invalidation Mode Select Register"]
129    #[inline(always)]
130    pub const fn iommu_tlb_ivld_mode_sel(&self) -> &IOMMU_TLB_IVLD_MODE_SEL {
131        &self.iommu_tlb_ivld_mode_sel
132    }
133    #[doc = "0x88 - IOMMU TLB Invalidation Start Address Register"]
134    #[inline(always)]
135    pub const fn iommu_tlb_ivld_sta_addr(&self) -> &IOMMU_TLB_IVLD_STA_ADDR {
136        &self.iommu_tlb_ivld_sta_addr
137    }
138    #[doc = "0x8c - IOMMU TLB Invalidation End Address Register"]
139    #[inline(always)]
140    pub const fn iommu_tlb_ivld_end_addr(&self) -> &IOMMU_TLB_IVLD_END_ADDR {
141        &self.iommu_tlb_ivld_end_addr
142    }
143    #[doc = "0x90 - IOMMU TLB Invalidation Address Register"]
144    #[inline(always)]
145    pub const fn iommu_tlb_ivld_addr(&self) -> &IOMMU_TLB_IVLD_ADDR {
146        &self.iommu_tlb_ivld_addr
147    }
148    #[doc = "0x94 - IOMMU TLB Invalidation Address Mask Register"]
149    #[inline(always)]
150    pub const fn iommu_tlb_ivld_addr_mask(&self) -> &IOMMU_TLB_IVLD_ADDR_MASK {
151        &self.iommu_tlb_ivld_addr_mask
152    }
153    #[doc = "0x98 - IOMMU TLB Invalidation Enable Register"]
154    #[inline(always)]
155    pub const fn iommu_tlb_ivld_enable(&self) -> &IOMMU_TLB_IVLD_ENABLE {
156        &self.iommu_tlb_ivld_enable
157    }
158    #[doc = "0x9c - IOMMU PC Invalidation Mode Select Register"]
159    #[inline(always)]
160    pub const fn iommu_pc_ivld_mode_sel(&self) -> &IOMMU_PC_IVLD_MODE_SEL {
161        &self.iommu_pc_ivld_mode_sel
162    }
163    #[doc = "0xa0 - IOMMU PC Invalidation Address Register"]
164    #[inline(always)]
165    pub const fn iommu_pc_ivld_addr(&self) -> &IOMMU_PC_IVLD_ADDR {
166        &self.iommu_pc_ivld_addr
167    }
168    #[doc = "0xa4 - IOMMU PC Invalidation Start Address Register"]
169    #[inline(always)]
170    pub const fn iommu_pc_ivld_sta_addr(&self) -> &IOMMU_PC_IVLD_STA_ADDR {
171        &self.iommu_pc_ivld_sta_addr
172    }
173    #[doc = "0xa8 - IOMMU PC Invalidation Enable Register"]
174    #[inline(always)]
175    pub const fn iommu_pc_ivld_enable(&self) -> &IOMMU_PC_IVLD_ENABLE {
176        &self.iommu_pc_ivld_enable
177    }
178    #[doc = "0xac - IOMMU PC Invalidation End Address Register"]
179    #[inline(always)]
180    pub const fn iommu_pc_ivld_end_addr(&self) -> &IOMMU_PC_IVLD_END_ADDR {
181        &self.iommu_pc_ivld_end_addr
182    }
183    #[doc = "0xb0..0xd0 - IOMMU Domain Authority Control \\[i\\] Register\n\nSoftware can set 15 different permission control types in IOMMU_DM_AUT_CTRL0-7. A default access control type is DOMAIN0. The read/write operation of DOMAIN1-15 is unlimited by default.\n\nSoftware needs to set the index of the permission control domain corresponding to the page table item in the bit\\[7:4\\] of the Level2 page table, the default value is 0 (use domain 0), that is, the read/write operation is not controlled.\n\nSetting REG_ARD_OVWT can mask the Domain control defined by IOMMU_DM_AUT_CTRL0-7. All Level2 page table type are covered by the type of REG_ARD_OVWT. The read/write operation is permitted by default."]
184    #[inline(always)]
185    pub const fn iommu_dm_aut_ctrl(&self, n: usize) -> &IOMMU_DM_AUT_CTRL {
186        &self.iommu_dm_aut_ctrl[n]
187    }
188    #[doc = "0xd0 - IOMMU Domain Authority Overwrite Register"]
189    #[inline(always)]
190    pub const fn iommu_dm_aut_ovwt(&self) -> &IOMMU_DM_AUT_OVWT {
191        &self.iommu_dm_aut_ovwt
192    }
193    #[doc = "0x100 - IOMMU Interrupt Enable Register"]
194    #[inline(always)]
195    pub const fn iommu_int_enable(&self) -> &IOMMU_INT_ENABLE {
196        &self.iommu_int_enable
197    }
198    #[doc = "0x104 - IOMMU Interrupt Clear Register"]
199    #[inline(always)]
200    pub const fn iommu_int_clr(&self) -> &IOMMU_INT_CLR {
201        &self.iommu_int_clr
202    }
203    #[doc = "0x108 - IOMMU Interrupt Status Register"]
204    #[inline(always)]
205    pub const fn iommu_int_sta(&self) -> &IOMMU_INT_STA {
206        &self.iommu_int_sta
207    }
208    #[doc = "0x110..0x12c - IOMMU Interrupt Error Address \\[i\\]"]
209    #[inline(always)]
210    pub const fn iommu_int_err_addr_tlb(&self, n: usize) -> &IOMMU_INT_ERR_ADDR_TLB {
211        &self.iommu_int_err_addr_tlb[n]
212    }
213    #[doc = "0x130..0x138 - IOMMU Interrupt Error Address L\\[i\\]"]
214    #[inline(always)]
215    pub const fn iommu_int_err_addr_l(&self, n: usize) -> &IOMMU_INT_ERR_ADDR_L {
216        &self.iommu_int_err_addr_l[n]
217    }
218    #[doc = "0x150..0x16c - IOMMU Interrupt Error Data \\[i\\] Register"]
219    #[inline(always)]
220    pub const fn iommu_int_err_data_tlb(&self, n: usize) -> &IOMMU_INT_ERR_DATA_TLB {
221        &self.iommu_int_err_data_tlb[n]
222    }
223    #[doc = "0x170..0x178 - IOMMU Interrupt Error Data L\\[i\\] Register"]
224    #[inline(always)]
225    pub const fn iommu_int_err_data_l(&self, n: usize) -> &IOMMU_INT_ERR_DATA_L {
226        &self.iommu_int_err_data_l[n]
227    }
228    #[doc = "0x180..0x188 - IOMMU L\\[i\\] Page Table Interrupt Register"]
229    #[inline(always)]
230    pub const fn iommu_lpg_int(&self, n: usize) -> &IOMMU_LPG_INT {
231        &self.iommu_lpg_int[n]
232    }
233    #[doc = "0x180 - IOMMU L\\[i\\] Page Table Interrupt Register"]
234    #[inline(always)]
235    pub const fn iommu_l0pg_int(&self) -> &IOMMU_LPG_INT {
236        self.iommu_lpg_int(0)
237    }
238    #[doc = "0x184 - IOMMU L\\[i\\] Page Table Interrupt Register"]
239    #[inline(always)]
240    pub const fn iommu_l1pg_int(&self) -> &IOMMU_LPG_INT {
241        self.iommu_lpg_int(1)
242    }
243    #[doc = "0x190 - IOMMU Virtual Address Register"]
244    #[inline(always)]
245    pub const fn iommu_va(&self) -> &IOMMU_VA {
246        &self.iommu_va
247    }
248    #[doc = "0x194 - IOMMU Virtual Address Data Register"]
249    #[inline(always)]
250    pub const fn iommu_va_data(&self) -> &IOMMU_VA_DATA {
251        &self.iommu_va_data
252    }
253    #[doc = "0x198 - IOMMU Virtual Address Configuration Register"]
254    #[inline(always)]
255    pub const fn iommu_va_config(&self) -> &IOMMU_VA_CONFIG {
256        &self.iommu_va_config
257    }
258    #[doc = "0x200 - IOMMU PMU Enable Register"]
259    #[inline(always)]
260    pub const fn iommu_pmu_enable(&self) -> &IOMMU_PMU_ENABLE {
261        &self.iommu_pmu_enable
262    }
263    #[doc = "0x210 - IOMMU PMU Clear Register"]
264    #[inline(always)]
265    pub const fn iommu_pmu_clr(&self) -> &IOMMU_PMU_CLR {
266        &self.iommu_pmu_clr
267    }
268    #[doc = "0x230..0x254 - IOMMU PMU Access Low \\[i\\] Register"]
269    #[inline(always)]
270    pub const fn iommu_pmu_access_low(&self, n: usize) -> &IOMMU_PMU_ACCESS_LOW {
271        #[allow(clippy::no_effect)]
272        [(); 9][n];
273        unsafe {
274            &*(self as *const Self)
275                .cast::<u8>()
276                .add(560)
277                .add(16 * n)
278                .cast()
279        }
280    }
281    #[doc = "0x234..0x258 - IOMMU PMU Access High \\[i\\] Register"]
282    #[inline(always)]
283    pub const fn iommu_pmu_access_high(&self, n: usize) -> &IOMMU_PMU_ACCESS_HIGH {
284        #[allow(clippy::no_effect)]
285        [(); 9][n];
286        unsafe {
287            &*(self as *const Self)
288                .cast::<u8>()
289                .add(564)
290                .add(16 * n)
291                .cast()
292        }
293    }
294    #[doc = "0x238..0x25c - IOMMU PMU Hit Low \\[i\\] Register"]
295    #[inline(always)]
296    pub const fn iommu_pmu_hit_low(&self, n: usize) -> &IOMMU_PMU_HIT_LOW {
297        #[allow(clippy::no_effect)]
298        [(); 9][n];
299        unsafe {
300            &*(self as *const Self)
301                .cast::<u8>()
302                .add(568)
303                .add(16 * n)
304                .cast()
305        }
306    }
307    #[doc = "0x23c..0x260 - IOMMU PMU Hit High \\[i\\] Register"]
308    #[inline(always)]
309    pub const fn iommu_pmu_hit_high(&self, n: usize) -> &IOMMU_PMU_HIT_HIGH {
310        #[allow(clippy::no_effect)]
311        [(); 9][n];
312        unsafe {
313            &*(self as *const Self)
314                .cast::<u8>()
315                .add(572)
316                .add(16 * n)
317                .cast()
318        }
319    }
320    #[doc = "0x300..0x31c - IOMMU Total Latency Low \\[i\\] Register"]
321    #[inline(always)]
322    pub const fn iommu_pmu_tl_low(&self, n: usize) -> &IOMMU_PMU_TL_LOW {
323        #[allow(clippy::no_effect)]
324        [(); 7][n];
325        unsafe {
326            &*(self as *const Self)
327                .cast::<u8>()
328                .add(768)
329                .add(16 * n)
330                .cast()
331        }
332    }
333    #[doc = "0x304..0x320 - IOMMU Total Latency High \\[i\\] Register"]
334    #[inline(always)]
335    pub const fn iommu_pmu_tl_high(&self, n: usize) -> &IOMMU_PMU_TL_HIGH {
336        #[allow(clippy::no_effect)]
337        [(); 7][n];
338        unsafe {
339            &*(self as *const Self)
340                .cast::<u8>()
341                .add(772)
342                .add(16 * n)
343                .cast()
344        }
345    }
346    #[doc = "0x308..0x324 - IOMMU Max Latency \\[i\\] Register"]
347    #[inline(always)]
348    pub const fn iommu_pmu_ml(&self, n: usize) -> &IOMMU_PMU_ML {
349        #[allow(clippy::no_effect)]
350        [(); 7][n];
351        unsafe {
352            &*(self as *const Self)
353                .cast::<u8>()
354                .add(776)
355                .add(16 * n)
356                .cast()
357        }
358    }
359}
360#[doc = "iommu_reset (rw) register accessor: IOMMU Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_reset::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_reset`] module"]
361pub type IOMMU_RESET = crate::Reg<iommu_reset::IOMMU_RESET_SPEC>;
362#[doc = "IOMMU Reset Register"]
363pub mod iommu_reset;
364#[doc = "iommu_enable (rw) register accessor: IOMMU Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_enable`] module"]
365pub type IOMMU_ENABLE = crate::Reg<iommu_enable::IOMMU_ENABLE_SPEC>;
366#[doc = "IOMMU Enable Register"]
367pub mod iommu_enable;
368#[doc = "iommu_bypass (rw) register accessor: IOMMU Bypass Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_bypass::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_bypass`] module"]
369pub type IOMMU_BYPASS = crate::Reg<iommu_bypass::IOMMU_BYPASS_SPEC>;
370#[doc = "IOMMU Bypass Register"]
371pub mod iommu_bypass;
372#[doc = "iommu_auto_gating (rw) register accessor: IOMMU Auto Gating Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_auto_gating::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_auto_gating::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_auto_gating`] module"]
373pub type IOMMU_AUTO_GATING = crate::Reg<iommu_auto_gating::IOMMU_AUTO_GATING_SPEC>;
374#[doc = "IOMMU Auto Gating Register"]
375pub mod iommu_auto_gating;
376#[doc = "iommu_wbuf_ctrl (rw) register accessor: IOMMU Write Buffer Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_wbuf_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_wbuf_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_wbuf_ctrl`] module"]
377pub type IOMMU_WBUF_CTRL = crate::Reg<iommu_wbuf_ctrl::IOMMU_WBUF_CTRL_SPEC>;
378#[doc = "IOMMU Write Buffer Control Register"]
379pub mod iommu_wbuf_ctrl;
380#[doc = "iommu_ooo_ctrl (rw) register accessor: IOMMU Out of Order Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_ooo_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_ooo_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_ooo_ctrl`] module"]
381pub type IOMMU_OOO_CTRL = crate::Reg<iommu_ooo_ctrl::IOMMU_OOO_CTRL_SPEC>;
382#[doc = "IOMMU Out of Order Control Register"]
383pub mod iommu_ooo_ctrl;
384#[doc = "iommu_4kb_bdy_prt_ctrl (rw) register accessor: IOMMU 4KB Boundary Protect Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_4kb_bdy_prt_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_4kb_bdy_prt_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_4kb_bdy_prt_ctrl`] module"]
385pub type IOMMU_4KB_BDY_PRT_CTRL = crate::Reg<iommu_4kb_bdy_prt_ctrl::IOMMU_4KB_BDY_PRT_CTRL_SPEC>;
386#[doc = "IOMMU 4KB Boundary Protect Control Register"]
387pub mod iommu_4kb_bdy_prt_ctrl;
388#[doc = "iommu_ttb (rw) register accessor: IOMMU Translation Table Base Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_ttb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_ttb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_ttb`] module"]
389pub type IOMMU_TTB = crate::Reg<iommu_ttb::IOMMU_TTB_SPEC>;
390#[doc = "IOMMU Translation Table Base Register"]
391pub mod iommu_ttb;
392#[doc = "iommu_tlb_enable (rw) register accessor: IOMMU TLB Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_tlb_enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_tlb_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_tlb_enable`] module"]
393pub type IOMMU_TLB_ENABLE = crate::Reg<iommu_tlb_enable::IOMMU_TLB_ENABLE_SPEC>;
394#[doc = "IOMMU TLB Enable Register"]
395pub mod iommu_tlb_enable;
396#[doc = "iommu_tlb_prefetch (rw) register accessor: IOMMU TLB Prefetch Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_tlb_prefetch::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_tlb_prefetch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_tlb_prefetch`] module"]
397pub type IOMMU_TLB_PREFETCH = crate::Reg<iommu_tlb_prefetch::IOMMU_TLB_PREFETCH_SPEC>;
398#[doc = "IOMMU TLB Prefetch Register"]
399pub mod iommu_tlb_prefetch;
400#[doc = "iommu_tlb_flush_enable (rw) register accessor: IOMMU TLB Flush Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_tlb_flush_enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_tlb_flush_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_tlb_flush_enable`] module"]
401pub type IOMMU_TLB_FLUSH_ENABLE = crate::Reg<iommu_tlb_flush_enable::IOMMU_TLB_FLUSH_ENABLE_SPEC>;
402#[doc = "IOMMU TLB Flush Enable Register"]
403pub mod iommu_tlb_flush_enable;
404#[doc = "iommu_tlb_ivld_mode_sel (rw) register accessor: IOMMU TLB Invalidation Mode Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_tlb_ivld_mode_sel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_tlb_ivld_mode_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_tlb_ivld_mode_sel`] module"]
405pub type IOMMU_TLB_IVLD_MODE_SEL =
406    crate::Reg<iommu_tlb_ivld_mode_sel::IOMMU_TLB_IVLD_MODE_SEL_SPEC>;
407#[doc = "IOMMU TLB Invalidation Mode Select Register"]
408pub mod iommu_tlb_ivld_mode_sel;
409#[doc = "iommu_tlb_ivld_sta_addr (rw) register accessor: IOMMU TLB Invalidation Start Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_tlb_ivld_sta_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_tlb_ivld_sta_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_tlb_ivld_sta_addr`] module"]
410pub type IOMMU_TLB_IVLD_STA_ADDR =
411    crate::Reg<iommu_tlb_ivld_sta_addr::IOMMU_TLB_IVLD_STA_ADDR_SPEC>;
412#[doc = "IOMMU TLB Invalidation Start Address Register"]
413pub mod iommu_tlb_ivld_sta_addr;
414#[doc = "iommu_tlb_ivld_end_addr (rw) register accessor: IOMMU TLB Invalidation End Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_tlb_ivld_end_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_tlb_ivld_end_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_tlb_ivld_end_addr`] module"]
415pub type IOMMU_TLB_IVLD_END_ADDR =
416    crate::Reg<iommu_tlb_ivld_end_addr::IOMMU_TLB_IVLD_END_ADDR_SPEC>;
417#[doc = "IOMMU TLB Invalidation End Address Register"]
418pub mod iommu_tlb_ivld_end_addr;
419#[doc = "iommu_tlb_ivld_addr (rw) register accessor: IOMMU TLB Invalidation Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_tlb_ivld_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_tlb_ivld_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_tlb_ivld_addr`] module"]
420pub type IOMMU_TLB_IVLD_ADDR = crate::Reg<iommu_tlb_ivld_addr::IOMMU_TLB_IVLD_ADDR_SPEC>;
421#[doc = "IOMMU TLB Invalidation Address Register"]
422pub mod iommu_tlb_ivld_addr;
423#[doc = "iommu_tlb_ivld_addr_mask (rw) register accessor: IOMMU TLB Invalidation Address Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_tlb_ivld_addr_mask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_tlb_ivld_addr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_tlb_ivld_addr_mask`] module"]
424pub type IOMMU_TLB_IVLD_ADDR_MASK =
425    crate::Reg<iommu_tlb_ivld_addr_mask::IOMMU_TLB_IVLD_ADDR_MASK_SPEC>;
426#[doc = "IOMMU TLB Invalidation Address Mask Register"]
427pub mod iommu_tlb_ivld_addr_mask;
428#[doc = "iommu_tlb_ivld_enable (rw) register accessor: IOMMU TLB Invalidation Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_tlb_ivld_enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_tlb_ivld_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_tlb_ivld_enable`] module"]
429pub type IOMMU_TLB_IVLD_ENABLE = crate::Reg<iommu_tlb_ivld_enable::IOMMU_TLB_IVLD_ENABLE_SPEC>;
430#[doc = "IOMMU TLB Invalidation Enable Register"]
431pub mod iommu_tlb_ivld_enable;
432#[doc = "iommu_pc_ivld_mode_sel (rw) register accessor: IOMMU PC Invalidation Mode Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pc_ivld_mode_sel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pc_ivld_mode_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_pc_ivld_mode_sel`] module"]
433pub type IOMMU_PC_IVLD_MODE_SEL = crate::Reg<iommu_pc_ivld_mode_sel::IOMMU_PC_IVLD_MODE_SEL_SPEC>;
434#[doc = "IOMMU PC Invalidation Mode Select Register"]
435pub mod iommu_pc_ivld_mode_sel;
436#[doc = "iommu_pc_ivld_addr (rw) register accessor: IOMMU PC Invalidation Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pc_ivld_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pc_ivld_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_pc_ivld_addr`] module"]
437pub type IOMMU_PC_IVLD_ADDR = crate::Reg<iommu_pc_ivld_addr::IOMMU_PC_IVLD_ADDR_SPEC>;
438#[doc = "IOMMU PC Invalidation Address Register"]
439pub mod iommu_pc_ivld_addr;
440#[doc = "iommu_pc_ivld_sta_addr (rw) register accessor: IOMMU PC Invalidation Start Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pc_ivld_sta_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pc_ivld_sta_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_pc_ivld_sta_addr`] module"]
441pub type IOMMU_PC_IVLD_STA_ADDR = crate::Reg<iommu_pc_ivld_sta_addr::IOMMU_PC_IVLD_STA_ADDR_SPEC>;
442#[doc = "IOMMU PC Invalidation Start Address Register"]
443pub mod iommu_pc_ivld_sta_addr;
444#[doc = "iommu_pc_ivld_enable (rw) register accessor: IOMMU PC Invalidation Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pc_ivld_enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pc_ivld_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_pc_ivld_enable`] module"]
445pub type IOMMU_PC_IVLD_ENABLE = crate::Reg<iommu_pc_ivld_enable::IOMMU_PC_IVLD_ENABLE_SPEC>;
446#[doc = "IOMMU PC Invalidation Enable Register"]
447pub mod iommu_pc_ivld_enable;
448#[doc = "iommu_pc_ivld_end_addr (rw) register accessor: IOMMU PC Invalidation End Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pc_ivld_end_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pc_ivld_end_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_pc_ivld_end_addr`] module"]
449pub type IOMMU_PC_IVLD_END_ADDR = crate::Reg<iommu_pc_ivld_end_addr::IOMMU_PC_IVLD_END_ADDR_SPEC>;
450#[doc = "IOMMU PC Invalidation End Address Register"]
451pub mod iommu_pc_ivld_end_addr;
452#[doc = "iommu_dm_aut_ctrl (rw) register accessor: IOMMU Domain Authority Control \\[i\\] Register\n\nSoftware can set 15 different permission control types in IOMMU_DM_AUT_CTRL0-7. A default access control type is DOMAIN0. The read/write operation of DOMAIN1-15 is unlimited by default.\n\nSoftware needs to set the index of the permission control domain corresponding to the page table item in the bit\\[7:4\\] of the Level2 page table, the default value is 0 (use domain 0), that is, the read/write operation is not controlled.\n\nSetting REG_ARD_OVWT can mask the Domain control defined by IOMMU_DM_AUT_CTRL0-7. All Level2 page table type are covered by the type of REG_ARD_OVWT. The read/write operation is permitted by default.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_dm_aut_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_dm_aut_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_dm_aut_ctrl`] module"]
453pub type IOMMU_DM_AUT_CTRL = crate::Reg<iommu_dm_aut_ctrl::IOMMU_DM_AUT_CTRL_SPEC>;
454#[doc = "IOMMU Domain Authority Control \\[i\\] Register\n\nSoftware can set 15 different permission control types in IOMMU_DM_AUT_CTRL0-7. A default access control type is DOMAIN0. The read/write operation of DOMAIN1-15 is unlimited by default.\n\nSoftware needs to set the index of the permission control domain corresponding to the page table item in the bit\\[7:4\\] of the Level2 page table, the default value is 0 (use domain 0), that is, the read/write operation is not controlled.\n\nSetting REG_ARD_OVWT can mask the Domain control defined by IOMMU_DM_AUT_CTRL0-7. All Level2 page table type are covered by the type of REG_ARD_OVWT. The read/write operation is permitted by default."]
455pub mod iommu_dm_aut_ctrl;
456#[doc = "iommu_dm_aut_ovwt (rw) register accessor: IOMMU Domain Authority Overwrite Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_dm_aut_ovwt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_dm_aut_ovwt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_dm_aut_ovwt`] module"]
457pub type IOMMU_DM_AUT_OVWT = crate::Reg<iommu_dm_aut_ovwt::IOMMU_DM_AUT_OVWT_SPEC>;
458#[doc = "IOMMU Domain Authority Overwrite Register"]
459pub mod iommu_dm_aut_ovwt;
460#[doc = "iommu_int_enable (rw) register accessor: IOMMU Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_int_enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_int_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_int_enable`] module"]
461pub type IOMMU_INT_ENABLE = crate::Reg<iommu_int_enable::IOMMU_INT_ENABLE_SPEC>;
462#[doc = "IOMMU Interrupt Enable Register"]
463pub mod iommu_int_enable;
464#[doc = "iommu_int_clr (rw) register accessor: IOMMU Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_int_clr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_int_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_int_clr`] module"]
465pub type IOMMU_INT_CLR = crate::Reg<iommu_int_clr::IOMMU_INT_CLR_SPEC>;
466#[doc = "IOMMU Interrupt Clear Register"]
467pub mod iommu_int_clr;
468#[doc = "iommu_int_sta (rw) register accessor: IOMMU Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_int_sta::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_int_sta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_int_sta`] module"]
469pub type IOMMU_INT_STA = crate::Reg<iommu_int_sta::IOMMU_INT_STA_SPEC>;
470#[doc = "IOMMU Interrupt Status Register"]
471pub mod iommu_int_sta;
472#[doc = "iommu_int_err_addr_tlb (r) register accessor: IOMMU Interrupt Error Address \\[i\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_int_err_addr_tlb::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_int_err_addr_tlb`] module"]
473pub type IOMMU_INT_ERR_ADDR_TLB = crate::Reg<iommu_int_err_addr_tlb::IOMMU_INT_ERR_ADDR_TLB_SPEC>;
474#[doc = "IOMMU Interrupt Error Address \\[i\\]"]
475pub mod iommu_int_err_addr_tlb;
476#[doc = "iommu_int_err_addr_l (r) register accessor: IOMMU Interrupt Error Address L\\[i\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_int_err_addr_l::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_int_err_addr_l`] module"]
477pub type IOMMU_INT_ERR_ADDR_L = crate::Reg<iommu_int_err_addr_l::IOMMU_INT_ERR_ADDR_L_SPEC>;
478#[doc = "IOMMU Interrupt Error Address L\\[i\\]"]
479pub mod iommu_int_err_addr_l;
480#[doc = "iommu_int_err_data_tlb (r) register accessor: IOMMU Interrupt Error Data \\[i\\] Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_int_err_data_tlb::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_int_err_data_tlb`] module"]
481pub type IOMMU_INT_ERR_DATA_TLB = crate::Reg<iommu_int_err_data_tlb::IOMMU_INT_ERR_DATA_TLB_SPEC>;
482#[doc = "IOMMU Interrupt Error Data \\[i\\] Register"]
483pub mod iommu_int_err_data_tlb;
484#[doc = "iommu_int_err_data_l (r) register accessor: IOMMU Interrupt Error Data L\\[i\\] Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_int_err_data_l::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_int_err_data_l`] module"]
485pub type IOMMU_INT_ERR_DATA_L = crate::Reg<iommu_int_err_data_l::IOMMU_INT_ERR_DATA_L_SPEC>;
486#[doc = "IOMMU Interrupt Error Data L\\[i\\] Register"]
487pub mod iommu_int_err_data_l;
488#[doc = "iommu_lpg_int (r) register accessor: IOMMU L\\[i\\] Page Table Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_lpg_int::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_lpg_int`] module"]
489pub type IOMMU_LPG_INT = crate::Reg<iommu_lpg_int::IOMMU_LPG_INT_SPEC>;
490#[doc = "IOMMU L\\[i\\] Page Table Interrupt Register"]
491pub mod iommu_lpg_int;
492#[doc = "iommu_va (rw) register accessor: IOMMU Virtual Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_va::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_va::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_va`] module"]
493pub type IOMMU_VA = crate::Reg<iommu_va::IOMMU_VA_SPEC>;
494#[doc = "IOMMU Virtual Address Register"]
495pub mod iommu_va;
496#[doc = "iommu_va_data (rw) register accessor: IOMMU Virtual Address Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_va_data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_va_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_va_data`] module"]
497pub type IOMMU_VA_DATA = crate::Reg<iommu_va_data::IOMMU_VA_DATA_SPEC>;
498#[doc = "IOMMU Virtual Address Data Register"]
499pub mod iommu_va_data;
500#[doc = "iommu_va_config (rw) register accessor: IOMMU Virtual Address Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_va_config::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_va_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_va_config`] module"]
501pub type IOMMU_VA_CONFIG = crate::Reg<iommu_va_config::IOMMU_VA_CONFIG_SPEC>;
502#[doc = "IOMMU Virtual Address Configuration Register"]
503pub mod iommu_va_config;
504#[doc = "iommu_pmu_enable (rw) register accessor: IOMMU PMU Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pmu_enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pmu_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_pmu_enable`] module"]
505pub type IOMMU_PMU_ENABLE = crate::Reg<iommu_pmu_enable::IOMMU_PMU_ENABLE_SPEC>;
506#[doc = "IOMMU PMU Enable Register"]
507pub mod iommu_pmu_enable;
508#[doc = "iommu_pmu_clr (rw) register accessor: IOMMU PMU Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pmu_clr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pmu_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_pmu_clr`] module"]
509pub type IOMMU_PMU_CLR = crate::Reg<iommu_pmu_clr::IOMMU_PMU_CLR_SPEC>;
510#[doc = "IOMMU PMU Clear Register"]
511pub mod iommu_pmu_clr;
512#[doc = "iommu_pmu_access_low (rw) register accessor: IOMMU PMU Access Low \\[i\\] Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pmu_access_low::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pmu_access_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_pmu_access_low`] module"]
513pub type IOMMU_PMU_ACCESS_LOW = crate::Reg<iommu_pmu_access_low::IOMMU_PMU_ACCESS_LOW_SPEC>;
514#[doc = "IOMMU PMU Access Low \\[i\\] Register"]
515pub mod iommu_pmu_access_low;
516#[doc = "iommu_pmu_access_high (rw) register accessor: IOMMU PMU Access High \\[i\\] Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pmu_access_high::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pmu_access_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_pmu_access_high`] module"]
517pub type IOMMU_PMU_ACCESS_HIGH = crate::Reg<iommu_pmu_access_high::IOMMU_PMU_ACCESS_HIGH_SPEC>;
518#[doc = "IOMMU PMU Access High \\[i\\] Register"]
519pub mod iommu_pmu_access_high;
520#[doc = "iommu_pmu_hit_low (rw) register accessor: IOMMU PMU Hit Low \\[i\\] Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pmu_hit_low::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pmu_hit_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_pmu_hit_low`] module"]
521pub type IOMMU_PMU_HIT_LOW = crate::Reg<iommu_pmu_hit_low::IOMMU_PMU_HIT_LOW_SPEC>;
522#[doc = "IOMMU PMU Hit Low \\[i\\] Register"]
523pub mod iommu_pmu_hit_low;
524#[doc = "iommu_pmu_hit_high (rw) register accessor: IOMMU PMU Hit High \\[i\\] Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pmu_hit_high::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pmu_hit_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_pmu_hit_high`] module"]
525pub type IOMMU_PMU_HIT_HIGH = crate::Reg<iommu_pmu_hit_high::IOMMU_PMU_HIT_HIGH_SPEC>;
526#[doc = "IOMMU PMU Hit High \\[i\\] Register"]
527pub mod iommu_pmu_hit_high;
528#[doc = "iommu_pmu_tl_low (rw) register accessor: IOMMU Total Latency Low \\[i\\] Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pmu_tl_low::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pmu_tl_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_pmu_tl_low`] module"]
529pub type IOMMU_PMU_TL_LOW = crate::Reg<iommu_pmu_tl_low::IOMMU_PMU_TL_LOW_SPEC>;
530#[doc = "IOMMU Total Latency Low \\[i\\] Register"]
531pub mod iommu_pmu_tl_low;
532#[doc = "iommu_pmu_tl_high (rw) register accessor: IOMMU Total Latency High \\[i\\] Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pmu_tl_high::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pmu_tl_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_pmu_tl_high`] module"]
533pub type IOMMU_PMU_TL_HIGH = crate::Reg<iommu_pmu_tl_high::IOMMU_PMU_TL_HIGH_SPEC>;
534#[doc = "IOMMU Total Latency High \\[i\\] Register"]
535pub mod iommu_pmu_tl_high;
536#[doc = "iommu_pmu_ml (rw) register accessor: IOMMU Max Latency \\[i\\] Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pmu_ml::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pmu_ml::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_pmu_ml`] module"]
537pub type IOMMU_PMU_ML = crate::Reg<iommu_pmu_ml::IOMMU_PMU_ML_SPEC>;
538#[doc = "IOMMU Max Latency \\[i\\] Register"]
539pub mod iommu_pmu_ml;
d1_pac/iommu.rs

d1_pac/
iommu.rs
