vj 0.2.0

vj: a SystemVerilog (IEEE 1800-2023) simulator built on slang and LLVM.
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//! `vj`'s library half: `run_design` (Task S7, ledger CG-125) lives
//! here so both `src/main.rs` (the `vj` CLI) and this crate's own
//! `tests/run_cli.rs` integration tests can call it directly, without
//! `tests/*.rs` needing to shell out to the built binary for anything but
//! the exit-code-behavior test (which explicitly wants to exercise the real
//! process, per the plan's own test spec).
pub mod aot;
pub(crate) mod aot_image;
pub(crate) mod aot_legacy;
pub mod aot_loader;
pub(crate) mod aot_sdf;
pub mod cli;
pub use vj_exec::verif::{AssertionReport, assertion_stats};
pub(crate) mod clocking;
pub(crate) mod constraint_decls;
pub(crate) mod covergroups;
pub(crate) mod decl_checks;
pub mod dpi;
pub mod dump;
pub(crate) mod fsmpragma;
pub(crate) mod interconnect;
pub mod kernel_prologue;
pub mod loader;
pub(crate) mod negtiming;
pub(crate) mod nets;
pub mod pipeline;
pub(crate) mod preproc;
pub(crate) mod primitives;
pub mod private_dir;
pub(crate) mod protect;
pub(crate) mod randseq;
pub mod run;
pub(crate) mod sdf_apply;
pub(crate) mod sdf_checks;
pub(crate) mod sdf_cond;
pub(crate) mod sdf_labels;
pub(crate) mod sdf_values;
pub mod sources;
pub(crate) mod specify;
pub(crate) mod specify_eval;
pub mod timing_options;
pub(crate) mod timingcheck;
pub(crate) mod usernets;
pub(crate) mod verif_image;
pub mod vpi;