vj 0.2.0

vj: a SystemVerilog (IEEE 1800-2023) simulator built on slang and LLVM.
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//! Interconnect delays (IEEE 1800-2023 32.4.4, Table 32-3; SD-C / T29): the delay
//! `$sdf_annotate`'s `PORT`, `NETDELAY` and `INTERCONNECT` constructs put between a net's source
//! and a load port. The delay lines themselves live in `vj-exec`
//! ([`vj_exec::timing::interconnect`], which the built AOT image runs too); `vj run`
//! plans the wires and builds them from here.

pub(crate) use vj_exec::timing::interconnect::{
    Meta, Node, SharedTable, WireInfo, WireSpec, new_table, register,
};