vj-sim 0.3.0

Netlist, scheduler and process model of the vj SystemVerilog simulator.
Documentation
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# vj-sim

Part of [vj](https://crates.io/crates/vj), a SystemVerilog (IEEE 1800-2023) simulator. See the `vj` crate for documentation.

Licensed under either of Apache License 2.0 or MIT license at your option.