[package]
edition = "2024"
rust-version = "1.97"
name = "vj-sim"
version = "0.3.0"
authors = ["Chaitanya Sharma"]
build = false
include = [
"src/**/*",
"build.rs",
"Cargo.toml",
"README.md",
"LICENSE-MIT",
"LICENSE-APACHE",
]
autolib = false
autobins = false
autoexamples = false
autotests = false
autobenches = false
description = "Netlist, scheduler and process model of the vj SystemVerilog simulator."
readme = "README.md"
keywords = [
"systemverilog",
"simulator",
"hdl",
"eda",
"verilog",
]
categories = [
"simulation",
"development-tools",
]
license = "MIT OR Apache-2.0"
resolver = "2"
[features]
aot-exports = []
default = ["frontend"]
frontend = [
"dep:sv-lang",
"dep:sv-lang-kinds",
]
[lib]
name = "vj_sim"
path = "src/lib.rs"
[dependencies.biodivine-lib-bdd]
version = "=0.6.3"
[dependencies.crossbeam-channel]
version = "0.5"
[dependencies.num-bigint]
version = "=0.4.8"
features = ["serde"]
[dependencies.num-traits]
version = "=0.2.19"
[dependencies.postcard]
version = "1"
features = ["alloc"]
default-features = false
[dependencies.rustc-hash]
version = "2"
[dependencies.serde]
version = "1"
features = ["derive"]
[dependencies.slotmap]
version = "1"
[dependencies.smallvec]
version = "1"
[dependencies.splr]
version = "=0.17.2"
[dependencies.sv-lang]
version = "=0.1.18"
optional = true
[dependencies.sv-lang-kinds]
version = "=0.1.2"
optional = true
[dependencies.vj-abi]
version = "0.3.0"
[dev-dependencies.sv-lang]
version = "=0.1.18"
[dev-dependencies.sv-lang-kinds]
version = "=0.1.2"