[package]
edition = "2024"
rust-version = "1.97"
name = "vj-codegen"
version = "0.3.0"
authors = ["Chaitanya Sharma"]
build = false
include = [
"src/**/*",
"build.rs",
"Cargo.toml",
"README.md",
"LICENSE-MIT",
"LICENSE-APACHE",
]
autolib = false
autobins = false
autoexamples = false
autotests = false
autobenches = false
description = "LLVM code generator of the vj SystemVerilog simulator."
readme = "README.md"
keywords = [
"systemverilog",
"simulator",
"hdl",
"eda",
"verilog",
]
categories = [
"simulation",
"development-tools",
]
license = "MIT OR Apache-2.0"
resolver = "2"
[lib]
name = "vj_codegen"
path = "src/lib.rs"
[dependencies.inkwell]
version = "0.10"
features = ["llvm22-1"]
[dependencies.libloading]
version = "0.8"
[dependencies.llvm-sys]
version = "221"
[dependencies.rayon]
version = "1.12"
[dependencies.sv-lang]
version = "=0.1.18"
[dependencies.sv-lang-kinds]
version = "=0.1.2"
[dependencies.vj-abi]
version = "0.3.0"
[dependencies.vj-exec]
version = "0.3.0"
[dependencies.vj-harness]
version = "0.3.0"
[dependencies.vj-runtime]
version = "0.3.0"
[dependencies.vj-sim]
version = "0.3.0"
[dev-dependencies.libloading]
version = "0.8"