tpu-sg2002 0.1.0

TPU driver in Rust for SG2002 SoC.
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89

//! Hardware register definitions for the SG2002 TPU.
//!
//! Based on: hal/mars/reg_tdma.h and hal/mars/reg_tiu.h

// ============================================================================
// TDMA (Tensor DMA) registers - from reg_tdma.h
// ============================================================================

pub const TDMA_DESC_REG_BYTES: u32 = 0x40;
pub const TDMA_ENGINE_DESCRIPTOR_NUM: u32 = TDMA_DESC_REG_BYTES >> 2; // 16
pub const TDMA_NUM_BASE_REGS: u32 = 0x8;

// Register offsets (base = TDMA_ENGINE_BASE_ADDR = 0)
pub const TDMA_CTRL: u32 = 0x0;
pub const TDMA_DES_BASE: u32 = 0x4;
pub const TDMA_INT_MASK: u32 = 0x8;
pub const TDMA_SYNC_STATUS: u32 = 0xC;
pub const TDMA_CMD_ACCP0: u32 = 0x10;
pub const TDMA_ARRAYBASE0_L: u32 = 0x70;
pub const TDMA_ARRAYBASE1_L: u32 = 0x74;
pub const TDMA_ARRAYBASE2_L: u32 = 0x78;
pub const TDMA_ARRAYBASE3_L: u32 = 0x7C;
pub const TDMA_ARRAYBASE4_L: u32 = 0x80;
pub const TDMA_ARRAYBASE5_L: u32 = 0x84;
pub const TDMA_ARRAYBASE6_L: u32 = 0x88;
pub const TDMA_ARRAYBASE7_L: u32 = 0x8C;
pub const TDMA_ARRAYBASE0_H: u32 = 0x90;
pub const TDMA_ARRAYBASE1_H: u32 = 0x94;
pub const TDMA_DEBUG_MODE: u32 = 0xA0;
pub const TDMA_DCM_DISABLE: u32 = 0xA4;
pub const TDMA_STATUS: u32 = 0xEC;

// TDMA control register bits
pub const TDMA_CTRL_ENABLE_BIT: u32 = 0;
pub const TDMA_CTRL_MODESEL_BIT: u32 = 1;
pub const TDMA_CTRL_RESET_SYNCID_BIT: u32 = 2;
pub const TDMA_CTRL_FORCE_1ARRAY: u32 = 5;
pub const TDMA_CTRL_FORCE_2ARRAY: u32 = 6;
pub const TDMA_CTRL_BURSTLEN_BIT: u32 = 8;
pub const TDMA_CTRL_64BYTE_ALIGN_EN: u32 = 10;
pub const TDMA_CTRL_INTRA_CMD_OFF: u32 = 13;
pub const TDMA_CTRL_DESNUM_BIT: u32 = 16;

// TDMA interrupt/status values
pub const TDMA_MASK_INIT: u32 = 0x20;
pub const TDMA_INT_EOD: u32 = 0x1;
pub const TDMA_INT_EOPMU: u32 = 0x8000;
pub const TDMA_ALL_IDLE: u32 = 0x1F;

// ============================================================================
// TIU (Tensor Instruction Unit) registers - from reg_tiu.h
// ============================================================================

pub const BDC_ENGINE_CMD_ALIGNED_BIT: u32 = 8;
pub const TIU_ENGINE_BASE_ADDR: u32 = 0;
pub const BD_CMD_BASE_ADDR: u32 = TIU_ENGINE_BASE_ADDR + 0x0;
pub const BD_CTRL_BASE_ADDR: u32 = TIU_ENGINE_BASE_ADDR + 0x100;

// BD control bits (offset from BD_CTRL_BASE_ADDR)
pub const BD_TPU_EN: u32 = 0;
pub const BD_LANE_NUM: u32 = 22;
pub const BD_DES_ADDR_VLD: u32 = 30;
pub const BD_INTR_ENABLE: u32 = 31;

/// TIU lane number configuration (TIU_LANNUM).
#[repr(u32)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum TiuLaneNum {
    Lane2 = 0x1,
    Lane4 = 0x2,
    Lane8 = 0x3,
    Lane16 = 0x4,
    Lane32 = 0x5,
    Lane64 = 0x6,
}

// ============================================================================
// PMU registers (offset from TDMA base)
// ============================================================================

pub const TPUPMU_CTRL: u32 = 0x200;
pub const TPUPMU_BUFBASE: u32 = 0x20C;
pub const TPUPMU_BUFSIZE: u32 = 0x210;

// ============================================================================
// CPU engine
// ============================================================================

pub const CPU_ENGINE_DESCRIPTOR_NUM: usize = 56;