topstitch 0.95.1

Stitch together Verilog modules with Rust
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92

// SPDX-License-Identifier: Apache-2.0

use indexmap::IndexMap;

use crate::{ConvertibleToModDef, Intf};

impl Intf {
    pub fn flip_to(&self, mod_def_or_mod_inst: &impl ConvertibleToModDef) -> Intf {
        let mut mapping = IndexMap::new();
        for (func_name, port_slice) in self.get_port_slices() {
            let port = mod_def_or_mod_inst
                .to_mod_def()
                .add_port(port_slice.port.name(), port_slice.port.io().flip());
            mapping.insert(func_name, (port.get_port_name(), port_slice.width() - 1, 0));
        }
        mod_def_or_mod_inst
            .to_mod_def()
            .def_intf(self.get_intf_name(), mapping);
        mod_def_or_mod_inst.get_intf(self.get_intf_name())
    }

    pub fn copy_to(&self, mod_def_or_mod_inst: &impl ConvertibleToModDef) -> Intf {
        let mut mapping = IndexMap::new();
        for (func_name, port_slice) in self.get_port_slices() {
            let port = mod_def_or_mod_inst.to_mod_def().add_port(
                port_slice.port.name(),
                port_slice.port.io().with_width(port_slice.width()),
            );
            mapping.insert(func_name, (port.get_port_name(), port_slice.width() - 1, 0));
        }
        mod_def_or_mod_inst
            .to_mod_def()
            .def_intf(self.get_intf_name(), mapping);
        mod_def_or_mod_inst.get_intf(self.get_intf_name())
    }

    pub fn copy_to_with_prefix(
        &self,
        mod_def_or_mod_inst: &impl ConvertibleToModDef,
        name: impl AsRef<str>,
        prefix: impl AsRef<str>,
    ) -> Intf {
        let mut mapping = IndexMap::new();
        for (func_name, port_slice) in self.get_port_slices() {
            let port_name = format!("{}{}", prefix.as_ref(), func_name);
            mod_def_or_mod_inst.to_mod_def().add_port(
                &port_name,
                port_slice.port.io().with_width(port_slice.width()),
            );
            mapping.insert(func_name, (port_name, port_slice.width() - 1, 0));
        }
        mod_def_or_mod_inst.to_mod_def().def_intf(&name, mapping);
        mod_def_or_mod_inst.get_intf(&name)
    }

    pub fn copy_to_with_name_underscore(
        &self,
        mod_def_or_mod_inst: &impl ConvertibleToModDef,
        name: impl AsRef<str>,
    ) -> Intf {
        let prefix = format!("{}_", name.as_ref());
        self.copy_to_with_prefix(mod_def_or_mod_inst, name, prefix)
    }

    pub fn flip_to_with_prefix(
        &self,
        mod_def_or_mod_inst: &impl ConvertibleToModDef,
        name: impl AsRef<str>,
        prefix: impl AsRef<str>,
    ) -> Intf {
        let mut mapping = IndexMap::new();
        for (func_name, port_slice) in self.get_port_slices() {
            let port_name = format!("{}{}", prefix.as_ref(), func_name);
            mod_def_or_mod_inst.to_mod_def().add_port(
                &port_name,
                port_slice.port.io().with_width(port_slice.width()).flip(),
            );
            mapping.insert(func_name, (port_name, port_slice.width() - 1, 0));
        }
        mod_def_or_mod_inst.to_mod_def().def_intf(&name, mapping);
        mod_def_or_mod_inst.get_intf(&name)
    }

    pub fn flip_to_with_name_underscore(
        &self,
        mod_def_or_mod_inst: &impl ConvertibleToModDef,
        name: impl AsRef<str>,
    ) -> Intf {
        let prefix = format!("{}_", name.as_ref());
        self.flip_to_with_prefix(mod_def_or_mod_inst, name, prefix)
    }
}