teensycore 0.1.0

A kernel for the teensy4.0 microcontroller
Documentation 
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MEMORY
{
    ITCM (rwx):   ORIGIN = 0x00000000, LENGTH = 512K
    DTCM (rwx):   ORIGIN = 0x20000000, LENGTH = 512K
    RAM (rwx):    ORIGIN = 0x20200000, LENGTH = 512K
    FLASH (rwx):  ORIGIN = 0x60000000, LENGTH = 1984K
}

ENTRY(ImageVectorTable)

SECTIONS
{

    .text.progmem : {
        KEEP(*(.flashconfig))
        FILL(0xFF)
        . = ORIGIN(FLASH) + 0x1000;
        KEEP(*(.ivt))
        KEEP(*(.bootdata))

        *(.progmem*)
        KEEP(*(.startup))
                . = ALIGN(4);
                KEEP(*(.init))
                __preinit_array_start = .;
                KEEP (*(.preinit_array))
                __preinit_array_end = .;
                __init_array_start = .;
                KEEP (*(.init_array))
                __init_array_end = .;
        . = ALIGN(16);
    } > FLASH

    .text.itcm : {
        . = . + 32; /* MPU to trap NULL pointer deref */
        *(.fastrun)
        *(.text*)
        . = ALIGN(16);
    } > ITCM  AT> FLASH

    .data : {
        *(.vectable)
        . = ALIGN(16);
        FILL(0x00)
        . += 4096;
        /* 
            So the USB peripheral requires the endpoints to be 2048 aligned
            for mysterious reasons.
        */        
        . = ALIGN(2048);
        *(.endpoint_queue) 
        FILL(0x00)
        . += 4096;
        . = ALIGN(4096);

        *(.rodata*)
        *(.data*)
    } > DTCM AT> FLASH


    .bss ALIGN(4) : {
        *(.bss*)
        *(COMMON)
        . = ALIGN(32);
        . = . + 32; /* MPU to trap stack overflow */
    } > DTCM

    .bss.dma (NOLOAD) : {
        *(.dmabuffers)
        . = ALIGN(4096);
        . += 20480;
        *(.descriptors)
    } > RAM

    _stext = ADDR(.text.itcm);
    _etext = ADDR(.text.itcm) + SIZEOF(.text.itcm);
    _stextload = LOADADDR(.text.itcm);

    _sdata = ADDR(.data);
    _edata = ADDR(.data) + SIZEOF(.data);
    _sdataload = LOADADDR(.data);

    _sbss = ADDR(.bss);
    _ebss = ADDR(.bss) + SIZEOF(.bss);

    _heap_start = ADDR(.bss.dma) + SIZEOF(.bss.dma);
    _heap_end = ORIGIN(RAM) + LENGTH(RAM);

    _vectable_addr = ADDR(.data);

    _itcm_block_count = (SIZEOF(.text.itcm) + 0x7FFE) >> 15;
    _flexram_bank_config = 0xAAAAAAAA | ((1 << (_itcm_block_count * 2)) - 1);
    _estack = ORIGIN(DTCM) + ((16 - _itcm_block_count) << 15);

    _flashimagelen = SIZEOF(.text.progmem) + SIZEOF(.text.itcm) + SIZEOF(.data);
    _teensy_model_identifier = 0x24;
    _data_size = SIZEOF(.data);
    
    .debug_info     0 : { *(.debug_info) }
    .debug_abbrev   0 : { *(.debug_abbrev) }
    .debug_line     0 : { *(.debug_line) }
    .debug_frame    0 : { *(.debug_frame) }
    .debug_str      0 : { *(.debug_str) }
    .debug_loc      0 : { *(.debug_loc) }

}