svd-generator 0.7.0

Converts device information from flattened device tree into an SVD description
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69

use crate::svd::register::{
    create_bit_range, create_enum_value, create_enum_values, create_field, create_field_constraint,
    create_field_enum, create_register, create_register_properties, create_write_constraint,
};
use crate::Result;

/// Creates a StarFive JH7110 SYS SYSCON SYSCFG 10 register.
pub fn create() -> Result<svd::RegisterCluster> {
    create_register(
        "sys_syscfg10",
        "SYS SYSCONSAIF SYSCFG 40",
        0x28,
        create_register_properties(32, 0x51e0_0000)?,
        Some(&[
            create_field_constraint(
                "pll1_frac",
                "PLL1 frac value.",
                create_bit_range("[23:0]")?,
                svd::Access::ReadWrite,
                create_write_constraint(0, 0xff_ffff)?,
                None,
            )?,
            create_field_constraint(
                "pll1_gvco_bias",
                "PLL1 GVCO bias.",
                create_bit_range("[25:24]")?,
                svd::Access::ReadWrite,
                create_write_constraint(0, 0x3)?,
                None,
            )?,
            create_field(
                "pll1_lock",
                "PLL1 lock.",
                create_bit_range("[26:26]")?,
                svd::Access::ReadOnly,
                None,
            )?,
            create_field_enum(
                "pll1_pd",
                "PLL1 PD enable setting - driving the register low turns PD `on`.",
                create_bit_range("[27:27]")?,
                svd::Access::ReadWrite,
                &[create_enum_values(&[
                    create_enum_value("on", "Enable the PLL0 PD", 0b0)?,
                    create_enum_value("off", "Disable the PLL0 PD", 0b1)?,
                ])?],
                None,
            )?,
            create_field_constraint(
                "pll1_postdiv1",
                "PLL1 postdiv1 value.",
                create_bit_range("[29:28]")?,
                svd::Access::ReadWrite,
                create_write_constraint(0, 0x3)?,
                None,
            )?,
            create_field_constraint(
                "pll1_postdiv2",
                "PLL1 postdiv2 value.",
                create_bit_range("[31:30]")?,
                svd::Access::ReadWrite,
                create_write_constraint(0, 0x3)?,
                None,
            )?,
        ]),
        None,
    )
    .map(svd::RegisterCluster::Register)
}