use super::{create_field_noc_bus_oic_evemon, create_fields_noc_bus_oic_evemon};
use crate::svd::register::{
create_bit_range, create_field, create_register, create_register_properties,
};
use crate::Result;
pub fn create() -> Result<svd::RegisterCluster> {
let mut fields = Vec::with_capacity(19);
fields.extend_from_slice(&[
create_field(
"pll2_prediv",
"",
create_bit_range("[5:0]")?,
svd::Access::ReadWrite,
None,
)?,
create_field(
"pll2_testen",
"",
create_bit_range("[6:6]")?,
svd::Access::ReadWrite,
None,
)?,
create_field(
"pll2_testsel",
"",
create_bit_range("[8:7]")?,
svd::Access::ReadWrite,
None,
)?,
create_field(
"pll_test_mode",
"PLL test mode, only used for PLL BIST through jtag2apb",
create_bit_range("[9:9]")?,
svd::Access::ReadWrite,
None,
)?,
create_field(
"audio_i2sdin_sel",
"",
create_bit_range("[17:10]")?,
svd::Access::ReadWrite,
None,
)?,
create_field(
"noc_bus_clock_gating_off",
"",
create_bit_range("[18:18]")?,
svd::Access::ReadWrite,
None,
)?,
]);
for idx in 0..6 {
fields.extend_from_slice(&create_fields_noc_bus_oic_evemon(idx, 19 + (idx * 2))?);
}
fields.push(create_field_noc_bus_oic_evemon(
"start",
6,
31,
svd::Access::ReadWrite,
)?);
Ok(svd::RegisterCluster::Register(create_register(
"sys_syscfg13",
"SYS SYSCONSAIF SYSCFG 52",
0x34,
create_register_properties(32, 0x1)?,
Some(fields.as_ref()),
None,
)?))
}