stm32mp1 0.16.0

Device support crates for STM32MP1 devices
Documentation 
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///Register `HCFG` reader
pub type R = crate::R<HCFGrs>;
///Register `HCFG` writer
pub type W = crate::W<HCFGrs>;
///Field `FSLSPCS` reader - FSLSPCS
pub type FSLSPCS_R = crate::FieldReader;
///Field `FSLSPCS` writer - FSLSPCS
pub type FSLSPCS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
///Field `FSLSS` reader - FSLSS
pub type FSLSS_R = crate::BitReader;
///Field `DESCDMA` reader - DESCDMA
pub type DESCDMA_R = crate::BitReader;
///Field `DESCDMA` writer - DESCDMA
pub type DESCDMA_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `FRLSTEN` reader - FRLSTEN
pub type FRLSTEN_R = crate::FieldReader;
///Field `FRLSTEN` writer - FRLSTEN
pub type FRLSTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
///Field `PERSSCHEDENA` reader - PERSSCHEDENA
pub type PERSSCHEDENA_R = crate::BitReader;
///Field `PERSSCHEDENA` writer - PERSSCHEDENA
pub type PERSSCHEDENA_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bits 0:1 - FSLSPCS
    #[inline(always)]
    pub fn fslspcs(&self) -> FSLSPCS_R {
        FSLSPCS_R::new((self.bits & 3) as u8)
    }
    ///Bit 2 - FSLSS
    #[inline(always)]
    pub fn fslss(&self) -> FSLSS_R {
        FSLSS_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 23 - DESCDMA
    #[inline(always)]
    pub fn descdma(&self) -> DESCDMA_R {
        DESCDMA_R::new(((self.bits >> 23) & 1) != 0)
    }
    ///Bits 24:25 - FRLSTEN
    #[inline(always)]
    pub fn frlsten(&self) -> FRLSTEN_R {
        FRLSTEN_R::new(((self.bits >> 24) & 3) as u8)
    }
    ///Bit 26 - PERSSCHEDENA
    #[inline(always)]
    pub fn persschedena(&self) -> PERSSCHEDENA_R {
        PERSSCHEDENA_R::new(((self.bits >> 26) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HCFG")
            .field("fslspcs", &self.fslspcs())
            .field("fslss", &self.fslss())
            .field("descdma", &self.descdma())
            .field("frlsten", &self.frlsten())
            .field("persschedena", &self.persschedena())
            .finish()
    }
}
impl W {
    ///Bits 0:1 - FSLSPCS
    #[inline(always)]
    pub fn fslspcs(&mut self) -> FSLSPCS_W<HCFGrs> {
        FSLSPCS_W::new(self, 0)
    }
    ///Bit 23 - DESCDMA
    #[inline(always)]
    pub fn descdma(&mut self) -> DESCDMA_W<HCFGrs> {
        DESCDMA_W::new(self, 23)
    }
    ///Bits 24:25 - FRLSTEN
    #[inline(always)]
    pub fn frlsten(&mut self) -> FRLSTEN_W<HCFGrs> {
        FRLSTEN_W::new(self, 24)
    }
    ///Bit 26 - PERSSCHEDENA
    #[inline(always)]
    pub fn persschedena(&mut self) -> PERSSCHEDENA_W<HCFGrs> {
        PERSSCHEDENA_W::new(self, 26)
    }
}
/**This register configures the core after power-on. Do not make changes to this register after initializing the host.

You can [`read`](crate::Reg::read) this register and get [`hcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32MP153.html#OTG:HCFG)*/
pub struct HCFGrs;
impl crate::RegisterSpec for HCFGrs {
    type Ux = u32;
}
///`read()` method returns [`hcfg::R`](R) reader structure
impl crate::Readable for HCFGrs {}
///`write(|w| ..)` method takes [`hcfg::W`](W) writer structure
impl crate::Writable for HCFGrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets HCFG to value 0
impl crate::Resettable for HCFGrs {}