#![no_main]
#![no_std]
use core::{
cell::RefCell,
sync::atomic::{AtomicU32, Ordering},
};
use cortex_m::{asm, interrupt::Mutex};
use cortex_m_rt::entry;
use log::info;
use pac::interrupt;
use stm32h7xx_hal::{pac, prelude::*, timer};
#[path = "utilities/logger.rs"]
mod logger;
static OVERFLOWS: AtomicU32 = AtomicU32::new(0);
static TIMER: Mutex<RefCell<Option<timer::Timer<pac::TIM2>>>> =
Mutex::new(RefCell::new(None));
#[entry]
fn main() -> ! {
logger::init();
let mut cp = cortex_m::Peripherals::take().unwrap();
let dp = pac::Peripherals::take().unwrap();
info!("Setup PWR... ");
let pwr = dp.PWR.constrain();
let pwrcfg = pwr.freeze();
info!("Setup RCC... ");
let rcc = dp.RCC.constrain();
let ccdr = rcc.sys_ck(100.MHz()).freeze(pwrcfg, &dp.SYSCFG);
info!("");
info!("stm32h7xx-hal example - Tick Timer");
info!("");
let mut timer =
dp.TIM2
.tick_timer(1.MHz(), ccdr.peripheral.TIM2, &ccdr.clocks);
timer.listen(timer::Event::TimeOut);
cortex_m::interrupt::free(|cs| {
TIMER.borrow(cs).replace(Some(timer));
});
unsafe {
cp.NVIC.set_priority(interrupt::TIM2, 1);
pac::NVIC::unmask(interrupt::TIM2);
}
loop {
info!("timestamp: {}", timestamp());
asm::delay(1000);
}
}
#[interrupt]
fn TIM2() {
OVERFLOWS.fetch_add(1, core::sync::atomic::Ordering::SeqCst);
cortex_m::interrupt::free(|cs| {
let mut rc = TIMER.borrow(cs).borrow_mut();
let timer = rc.as_mut().unwrap();
timer.clear_irq();
})
}
pub fn timestamp() -> u64 {
let overflows = OVERFLOWS.load(Ordering::SeqCst) as u64;
let ctr = cortex_m::interrupt::free(|cs| {
let rc = TIMER.borrow(cs).borrow();
let timer = rc.as_ref().unwrap();
timer.counter() as u64
});
(overflows << 32) + ctr
}