stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

///Register `APB1HRSTR` reader
pub type R = crate::R<APB1HRSTRrs>;
///Register `APB1HRSTR` writer
pub type W = crate::W<APB1HRSTRrs>;
/**clock recovery system reset Set and reset by software.

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CRSRST {
    ///1: Reset the selected module
    Reset = 1,
}
impl From<CRSRST> for bool {
    #[inline(always)]
    fn from(variant: CRSRST) -> Self {
        variant as u8 != 0
    }
}
///Field `CRSRST` reader - clock recovery system reset Set and reset by software.
pub type CRSRST_R = crate::BitReader<CRSRST>;
impl CRSRST_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> Option<CRSRST> {
        match self.bits {
            true => Some(CRSRST::Reset),
            _ => None,
        }
    }
    ///Reset the selected module
    #[inline(always)]
    pub fn is_reset(&self) -> bool {
        *self == CRSRST::Reset
    }
}
///Field `CRSRST` writer - clock recovery system reset Set and reset by software.
pub type CRSRST_W<'a, REG> = crate::BitWriter<'a, REG, CRSRST>;
impl<'a, REG> CRSRST_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///Reset the selected module
    #[inline(always)]
    pub fn reset(self) -> &'a mut crate::W<REG> {
        self.variant(CRSRST::Reset)
    }
}
///Field `SWPMIRST` reader - SWPMI block reset Set and reset by software.
pub use CRSRST_R as SWPMIRST_R;
///Field `OPAMPRST` reader - OPAMP block reset Set and reset by software.
pub use CRSRST_R as OPAMPRST_R;
///Field `MDIOSRST` reader - MDIOS block reset Set and reset by software.
pub use CRSRST_R as MDIOSRST_R;
///Field `FDCANRST` reader - FDCAN block reset Set and reset by software.
pub use CRSRST_R as FDCANRST_R;
///Field `SWPMIRST` writer - SWPMI block reset Set and reset by software.
pub use CRSRST_W as SWPMIRST_W;
///Field `OPAMPRST` writer - OPAMP block reset Set and reset by software.
pub use CRSRST_W as OPAMPRST_W;
///Field `MDIOSRST` writer - MDIOS block reset Set and reset by software.
pub use CRSRST_W as MDIOSRST_W;
///Field `FDCANRST` writer - FDCAN block reset Set and reset by software.
pub use CRSRST_W as FDCANRST_W;
impl R {
    ///Bit 1 - clock recovery system reset Set and reset by software.
    #[inline(always)]
    pub fn crsrst(&self) -> CRSRST_R {
        CRSRST_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - SWPMI block reset Set and reset by software.
    #[inline(always)]
    pub fn swpmirst(&self) -> SWPMIRST_R {
        SWPMIRST_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 4 - OPAMP block reset Set and reset by software.
    #[inline(always)]
    pub fn opamprst(&self) -> OPAMPRST_R {
        OPAMPRST_R::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - MDIOS block reset Set and reset by software.
    #[inline(always)]
    pub fn mdiosrst(&self) -> MDIOSRST_R {
        MDIOSRST_R::new(((self.bits >> 5) & 1) != 0)
    }
    ///Bit 8 - FDCAN block reset Set and reset by software.
    #[inline(always)]
    pub fn fdcanrst(&self) -> FDCANRST_R {
        FDCANRST_R::new(((self.bits >> 8) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("APB1HRSTR")
            .field("crsrst", &self.crsrst())
            .field("swpmirst", &self.swpmirst())
            .field("opamprst", &self.opamprst())
            .field("mdiosrst", &self.mdiosrst())
            .field("fdcanrst", &self.fdcanrst())
            .finish()
    }
}
impl W {
    ///Bit 1 - clock recovery system reset Set and reset by software.
    #[inline(always)]
    pub fn crsrst(&mut self) -> CRSRST_W<APB1HRSTRrs> {
        CRSRST_W::new(self, 1)
    }
    ///Bit 2 - SWPMI block reset Set and reset by software.
    #[inline(always)]
    pub fn swpmirst(&mut self) -> SWPMIRST_W<APB1HRSTRrs> {
        SWPMIRST_W::new(self, 2)
    }
    ///Bit 4 - OPAMP block reset Set and reset by software.
    #[inline(always)]
    pub fn opamprst(&mut self) -> OPAMPRST_W<APB1HRSTRrs> {
        OPAMPRST_W::new(self, 4)
    }
    ///Bit 5 - MDIOS block reset Set and reset by software.
    #[inline(always)]
    pub fn mdiosrst(&mut self) -> MDIOSRST_W<APB1HRSTRrs> {
        MDIOSRST_W::new(self, 5)
    }
    ///Bit 8 - FDCAN block reset Set and reset by software.
    #[inline(always)]
    pub fn fdcanrst(&mut self) -> FDCANRST_W<APB1HRSTRrs> {
        FDCANRST_W::new(self, 8)
    }
}
/**

You can [`read`](crate::Reg::read) this register and get [`apb1hrstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1hrstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct APB1HRSTRrs;
impl crate::RegisterSpec for APB1HRSTRrs {
    type Ux = u32;
}
///`read()` method returns [`apb1hrstr::R`](R) reader structure
impl crate::Readable for APB1HRSTRrs {}
///`write(|w| ..)` method takes [`apb1hrstr::W`](W) writer structure
impl crate::Writable for APB1HRSTRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets APB1HRSTR to value 0
impl crate::Resettable for APB1HRSTRrs {}