stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
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///Register `AHB1LPENR` reader
pub type R = crate::R<AHB1LPENRrs>;
///Register `AHB1LPENR` writer
pub type W = crate::W<AHB1LPENRrs>;
/**DMA1 clock enable during CSleep mode Set and reset by software.

Value on reset: 1*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum DMA1LPEN {
    ///0: The selected clock is disabled during csleep mode
    Disabled = 0,
    ///1: The selected clock is enabled during csleep mode
    Enabled = 1,
}
impl From<DMA1LPEN> for bool {
    #[inline(always)]
    fn from(variant: DMA1LPEN) -> Self {
        variant as u8 != 0
    }
}
///Field `DMA1LPEN` reader - DMA1 clock enable during CSleep mode Set and reset by software.
pub type DMA1LPEN_R = crate::BitReader<DMA1LPEN>;
impl DMA1LPEN_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> DMA1LPEN {
        match self.bits {
            false => DMA1LPEN::Disabled,
            true => DMA1LPEN::Enabled,
        }
    }
    ///The selected clock is disabled during csleep mode
    #[inline(always)]
    pub fn is_disabled(&self) -> bool {
        *self == DMA1LPEN::Disabled
    }
    ///The selected clock is enabled during csleep mode
    #[inline(always)]
    pub fn is_enabled(&self) -> bool {
        *self == DMA1LPEN::Enabled
    }
}
///Field `DMA1LPEN` writer - DMA1 clock enable during CSleep mode Set and reset by software.
pub type DMA1LPEN_W<'a, REG> = crate::BitWriter<'a, REG, DMA1LPEN>;
impl<'a, REG> DMA1LPEN_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///The selected clock is disabled during csleep mode
    #[inline(always)]
    pub fn disabled(self) -> &'a mut crate::W<REG> {
        self.variant(DMA1LPEN::Disabled)
    }
    ///The selected clock is enabled during csleep mode
    #[inline(always)]
    pub fn enabled(self) -> &'a mut crate::W<REG> {
        self.variant(DMA1LPEN::Enabled)
    }
}
///Field `DMA2LPEN` reader - DMA2 clock enable during CSleep mode Set and reset by software.
pub use DMA1LPEN_R as DMA2LPEN_R;
///Field `ADC12LPEN` reader - ADC1 and 2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk1 bus interface clock.
pub use DMA1LPEN_R as ADC12LPEN_R;
///Field `CRCLPEN` reader - CRC peripheral clock enable during CSleep mode Set and reset by software.
pub use DMA1LPEN_R as CRCLPEN_R;
///Field `USB1OTGLPEN` reader - USB1OTG peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USB1OTG are the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock.
pub use DMA1LPEN_R as USB1OTGLPEN_R;
///Field `USB1OTGULPILPEN` reader - USB_PHY1 clock enable during CSleep mode Set and reset by software.
pub use DMA1LPEN_R as USB1OTGULPILPEN_R;
///Field `DMA2LPEN` writer - DMA2 clock enable during CSleep mode Set and reset by software.
pub use DMA1LPEN_W as DMA2LPEN_W;
///Field `ADC12LPEN` writer - ADC1 and 2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk1 bus interface clock.
pub use DMA1LPEN_W as ADC12LPEN_W;
///Field `CRCLPEN` writer - CRC peripheral clock enable during CSleep mode Set and reset by software.
pub use DMA1LPEN_W as CRCLPEN_W;
///Field `USB1OTGLPEN` writer - USB1OTG peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USB1OTG are the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock.
pub use DMA1LPEN_W as USB1OTGLPEN_W;
///Field `USB1OTGULPILPEN` writer - USB_PHY1 clock enable during CSleep mode Set and reset by software.
pub use DMA1LPEN_W as USB1OTGULPILPEN_W;
impl R {
    ///Bit 0 - DMA1 clock enable during CSleep mode Set and reset by software.
    #[inline(always)]
    pub fn dma1lpen(&self) -> DMA1LPEN_R {
        DMA1LPEN_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - DMA2 clock enable during CSleep mode Set and reset by software.
    #[inline(always)]
    pub fn dma2lpen(&self) -> DMA2LPEN_R {
        DMA2LPEN_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 5 - ADC1 and 2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk1 bus interface clock.
    #[inline(always)]
    pub fn adc12lpen(&self) -> ADC12LPEN_R {
        ADC12LPEN_R::new(((self.bits >> 5) & 1) != 0)
    }
    ///Bit 9 - CRC peripheral clock enable during CSleep mode Set and reset by software.
    #[inline(always)]
    pub fn crclpen(&self) -> CRCLPEN_R {
        CRCLPEN_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 25 - USB1OTG peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USB1OTG are the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock.
    #[inline(always)]
    pub fn usb1otglpen(&self) -> USB1OTGLPEN_R {
        USB1OTGLPEN_R::new(((self.bits >> 25) & 1) != 0)
    }
    ///Bit 26 - USB_PHY1 clock enable during CSleep mode Set and reset by software.
    #[inline(always)]
    pub fn usb1otgulpilpen(&self) -> USB1OTGULPILPEN_R {
        USB1OTGULPILPEN_R::new(((self.bits >> 26) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("AHB1LPENR")
            .field("dma1lpen", &self.dma1lpen())
            .field("dma2lpen", &self.dma2lpen())
            .field("adc12lpen", &self.adc12lpen())
            .field("crclpen", &self.crclpen())
            .field("usb1otglpen", &self.usb1otglpen())
            .field("usb1otgulpilpen", &self.usb1otgulpilpen())
            .finish()
    }
}
impl W {
    ///Bit 0 - DMA1 clock enable during CSleep mode Set and reset by software.
    #[inline(always)]
    pub fn dma1lpen(&mut self) -> DMA1LPEN_W<AHB1LPENRrs> {
        DMA1LPEN_W::new(self, 0)
    }
    ///Bit 1 - DMA2 clock enable during CSleep mode Set and reset by software.
    #[inline(always)]
    pub fn dma2lpen(&mut self) -> DMA2LPEN_W<AHB1LPENRrs> {
        DMA2LPEN_W::new(self, 1)
    }
    ///Bit 5 - ADC1 and 2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk1 bus interface clock.
    #[inline(always)]
    pub fn adc12lpen(&mut self) -> ADC12LPEN_W<AHB1LPENRrs> {
        ADC12LPEN_W::new(self, 5)
    }
    ///Bit 9 - CRC peripheral clock enable during CSleep mode Set and reset by software.
    #[inline(always)]
    pub fn crclpen(&mut self) -> CRCLPEN_W<AHB1LPENRrs> {
        CRCLPEN_W::new(self, 9)
    }
    ///Bit 25 - USB1OTG peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USB1OTG are the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock.
    #[inline(always)]
    pub fn usb1otglpen(&mut self) -> USB1OTGLPEN_W<AHB1LPENRrs> {
        USB1OTGLPEN_W::new(self, 25)
    }
    ///Bit 26 - USB_PHY1 clock enable during CSleep mode Set and reset by software.
    #[inline(always)]
    pub fn usb1otgulpilpen(&mut self) -> USB1OTGULPILPEN_W<AHB1LPENRrs> {
        USB1OTGULPILPEN_W::new(self, 26)
    }
}
/**

You can [`read`](crate::Reg::read) this register and get [`ahb1lpenr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb1lpenr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct AHB1LPENRrs;
impl crate::RegisterSpec for AHB1LPENRrs {
    type Ux = u32;
}
///`read()` method returns [`ahb1lpenr::R`](R) reader structure
impl crate::Readable for AHB1LPENRrs {}
///`write(|w| ..)` method takes [`ahb1lpenr::W`](W) writer structure
impl crate::Writable for AHB1LPENRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets AHB1LPENR to value 0x0600_0223
impl crate::Resettable for AHB1LPENRrs {
    const RESET_VALUE: u32 = 0x0600_0223;
}