stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119

///Register `CR` reader
pub type R = crate::R<CRrs>;
///Register `CR` writer
pub type W = crate::W<CRrs>;
///Field `EN` reader - peripheral enable
pub type EN_R = crate::BitReader;
///Field `EN` writer - peripheral enable
pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `WRIE` reader - register write interrupt enable Note: When this bit is set, an interrupt is generated if any of the read flags (WRF\[31:0\] in the MDIOS_WRFR register) is set.
pub type WRIE_R = crate::BitReader;
///Field `WRIE` writer - register write interrupt enable Note: When this bit is set, an interrupt is generated if any of the read flags (WRF\[31:0\] in the MDIOS_WRFR register) is set.
pub type WRIE_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `RDIE` reader - register read interrupt enable Note: When this bit is set, an interrupt is generated if any of the read flags (RDF\[31:0\] in the MDIOS_RDFR register) is set.
pub type RDIE_R = crate::BitReader;
///Field `RDIE` writer - register read interrupt enable Note: When this bit is set, an interrupt is generated if any of the read flags (RDF\[31:0\] in the MDIOS_RDFR register) is set.
pub type RDIE_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `EIE` reader - error interrupt enable Note: When this bit is set, an interrupt is generated if any of the error flags (PERF, SERF, or TERF in the MDIOS_SR register) is set.
pub type EIE_R = crate::BitReader;
///Field `EIE` writer - error interrupt enable Note: When this bit is set, an interrupt is generated if any of the error flags (PERF, SERF, or TERF in the MDIOS_SR register) is set.
pub type EIE_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `DPC` reader - disable preamble check Note: When this bit is set, the application must be sure that no frame is currently in progress when the MDIOS is enabled. Otherwise, the MDIOS can become desynchronized with the master. Note: This bit cannot be changed unless EN = 0 (though it can be changed at the same time that EN is being set).
pub type DPC_R = crate::BitReader;
///Field `DPC` writer - disable preamble check Note: When this bit is set, the application must be sure that no frame is currently in progress when the MDIOS is enabled. Otherwise, the MDIOS can become desynchronized with the master. Note: This bit cannot be changed unless EN = 0 (though it can be changed at the same time that EN is being set).
pub type DPC_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `PORT_ADDRESS` reader - slave address Can be written only when the peripheral is disabled (EN = 0). If the address given by the MDIO master matches PORT_ADRESS\[4:0\], then the MDIOS services the frame. Otherwise the frame is ignored.
pub type PORT_ADDRESS_R = crate::FieldReader;
///Field `PORT_ADDRESS` writer - slave address Can be written only when the peripheral is disabled (EN = 0). If the address given by the MDIO master matches PORT_ADRESS\[4:0\], then the MDIOS services the frame. Otherwise the frame is ignored.
pub type PORT_ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
impl R {
    ///Bit 0 - peripheral enable
    #[inline(always)]
    pub fn en(&self) -> EN_R {
        EN_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - register write interrupt enable Note: When this bit is set, an interrupt is generated if any of the read flags (WRF\[31:0\] in the MDIOS_WRFR register) is set.
    #[inline(always)]
    pub fn wrie(&self) -> WRIE_R {
        WRIE_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - register read interrupt enable Note: When this bit is set, an interrupt is generated if any of the read flags (RDF\[31:0\] in the MDIOS_RDFR register) is set.
    #[inline(always)]
    pub fn rdie(&self) -> RDIE_R {
        RDIE_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - error interrupt enable Note: When this bit is set, an interrupt is generated if any of the error flags (PERF, SERF, or TERF in the MDIOS_SR register) is set.
    #[inline(always)]
    pub fn eie(&self) -> EIE_R {
        EIE_R::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 7 - disable preamble check Note: When this bit is set, the application must be sure that no frame is currently in progress when the MDIOS is enabled. Otherwise, the MDIOS can become desynchronized with the master. Note: This bit cannot be changed unless EN = 0 (though it can be changed at the same time that EN is being set).
    #[inline(always)]
    pub fn dpc(&self) -> DPC_R {
        DPC_R::new(((self.bits >> 7) & 1) != 0)
    }
    ///Bits 8:12 - slave address Can be written only when the peripheral is disabled (EN = 0). If the address given by the MDIO master matches PORT_ADRESS\[4:0\], then the MDIOS services the frame. Otherwise the frame is ignored.
    #[inline(always)]
    pub fn port_address(&self) -> PORT_ADDRESS_R {
        PORT_ADDRESS_R::new(((self.bits >> 8) & 0x1f) as u8)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CR")
            .field("en", &self.en())
            .field("wrie", &self.wrie())
            .field("rdie", &self.rdie())
            .field("eie", &self.eie())
            .field("dpc", &self.dpc())
            .field("port_address", &self.port_address())
            .finish()
    }
}
impl W {
    ///Bit 0 - peripheral enable
    #[inline(always)]
    pub fn en(&mut self) -> EN_W<CRrs> {
        EN_W::new(self, 0)
    }
    ///Bit 1 - register write interrupt enable Note: When this bit is set, an interrupt is generated if any of the read flags (WRF\[31:0\] in the MDIOS_WRFR register) is set.
    #[inline(always)]
    pub fn wrie(&mut self) -> WRIE_W<CRrs> {
        WRIE_W::new(self, 1)
    }
    ///Bit 2 - register read interrupt enable Note: When this bit is set, an interrupt is generated if any of the read flags (RDF\[31:0\] in the MDIOS_RDFR register) is set.
    #[inline(always)]
    pub fn rdie(&mut self) -> RDIE_W<CRrs> {
        RDIE_W::new(self, 2)
    }
    ///Bit 3 - error interrupt enable Note: When this bit is set, an interrupt is generated if any of the error flags (PERF, SERF, or TERF in the MDIOS_SR register) is set.
    #[inline(always)]
    pub fn eie(&mut self) -> EIE_W<CRrs> {
        EIE_W::new(self, 3)
    }
    ///Bit 7 - disable preamble check Note: When this bit is set, the application must be sure that no frame is currently in progress when the MDIOS is enabled. Otherwise, the MDIOS can become desynchronized with the master. Note: This bit cannot be changed unless EN = 0 (though it can be changed at the same time that EN is being set).
    #[inline(always)]
    pub fn dpc(&mut self) -> DPC_W<CRrs> {
        DPC_W::new(self, 7)
    }
    ///Bits 8:12 - slave address Can be written only when the peripheral is disabled (EN = 0). If the address given by the MDIO master matches PORT_ADRESS\[4:0\], then the MDIOS services the frame. Otherwise the frame is ignored.
    #[inline(always)]
    pub fn port_address(&mut self) -> PORT_ADDRESS_W<CRrs> {
        PORT_ADDRESS_W::new(self, 8)
    }
}
/**MDIOS configuration register

You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct CRrs;
impl crate::RegisterSpec for CRrs {
    type Ux = u32;
}
///`read()` method returns [`cr::R`](R) reader structure
impl crate::Readable for CRrs {}
///`write(|w| ..)` method takes [`cr::W`](W) writer structure
impl crate::Writable for CRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets CR to value 0
impl crate::Resettable for CRrs {}