stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

///Register `WDGPAR` reader
pub type R = crate::R<WDGPARrs>;
///Register `WDGPAR` writer
pub type W = crate::W<WDGPARrs>;
///Field `PREALARM` reader - pre-alarm value Pre-alarm value of the watchdog counter.
pub type PREALARM_R = crate::FieldReader<u16>;
///Field `PREALARM` writer - pre-alarm value Pre-alarm value of the watchdog counter.
pub type PREALARM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
    ///Bits 0:15 - pre-alarm value Pre-alarm value of the watchdog counter.
    #[inline(always)]
    pub fn prealarm(&self) -> PREALARM_R {
        PREALARM_R::new((self.bits & 0xffff) as u16)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("WDGPAR").field("prealarm", &self.prealarm()).finish()
    }
}
impl W {
    ///Bits 0:15 - pre-alarm value Pre-alarm value of the watchdog counter.
    #[inline(always)]
    pub fn prealarm(&mut self) -> PREALARM_W<WDGPARrs> {
        PREALARM_W::new(self, 0)
    }
}
/**GFXTIM watchdog pre-alarm register

You can [`read`](crate::Reg::read) this register and get [`wdgpar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdgpar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct WDGPARrs;
impl crate::RegisterSpec for WDGPARrs {
    type Ux = u32;
}
///`read()` method returns [`wdgpar::R`](R) reader structure
impl crate::Readable for WDGPARrs {}
///`write(|w| ..)` method takes [`wdgpar::W`](W) writer structure
impl crate::Writable for WDGPARrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets WDGPAR to value 0
impl crate::Resettable for WDGPARrs {}